"Power domain maintenance" updates from v4.9/rcar-3.5.9 branch

drivers/soc/renesas/r8a7795-sysc.c

@@ -37,17 +37,23 @@ static const struct rcar_sysc_area r8a7795_areas[] __initconst = {
 	  PD_CPU_NOCR },
 	{ "ca53-cpu3",	0x200, 3, R8A7795_PD_CA53_CPU3,	R8A7795_PD_CA53_SCU,
 	  PD_CPU_NOCR },
-	{ "a3vp",	0x340, 0, R8A7795_PD_A3VP,	R8A7795_PD_ALWAYS_ON },
-	{ "cr7",	0x240, 0, R8A7795_PD_CR7,	R8A7795_PD_ALWAYS_ON },
-	{ "a3vc",	0x380, 0, R8A7795_PD_A3VC,	R8A7795_PD_ALWAYS_ON },
-	{ "a2vc0",	0x3c0, 0, R8A7795_PD_A2VC0,	R8A7795_PD_A3VC },
-	{ "a2vc1",	0x3c0, 1, R8A7795_PD_A2VC1,	R8A7795_PD_A3VC },
+	{ "a3vp",	0x340, 0, R8A7795_PD_A3VP,	R8A7795_PD_ALWAYS_ON,
+	  (PD_NO_CR | PD_ON_ONCE) },
+	{ "cr7",	0x240, 0, R8A7795_PD_CR7,	R8A7795_PD_ALWAYS_ON,
+	  (PD_NO_CR | PD_ON_ONCE) },
+	{ "a3vc",	0x380, 0, R8A7795_PD_A3VC,	R8A7795_PD_ALWAYS_ON,
+	  (PD_NO_CR | PD_ON_ONCE) },
+	{ "a2vc0",	0x3c0, 0, R8A7795_PD_A2VC0,	R8A7795_PD_A3VC,
+	  (PD_NO_CR | PD_ON_ONCE) },
+	{ "a2vc1",	0x3c0, 1, R8A7795_PD_A2VC1,	R8A7795_PD_A3VC,
+	  (PD_NO_CR | PD_ON_ONCE) },
 	{ "3dg-a",	0x100, 0, R8A7795_PD_3DG_A,	R8A7795_PD_ALWAYS_ON },
 	{ "3dg-b",	0x100, 1, R8A7795_PD_3DG_B,	R8A7795_PD_3DG_A },
 	{ "3dg-c",	0x100, 2, R8A7795_PD_3DG_C,	R8A7795_PD_3DG_B },
 	{ "3dg-d",	0x100, 3, R8A7795_PD_3DG_D,	R8A7795_PD_3DG_C },
 	{ "3dg-e",	0x100, 4, R8A7795_PD_3DG_E,	R8A7795_PD_3DG_D },
-	{ "a3ir",	0x180, 0, R8A7795_PD_A3IR,	R8A7795_PD_ALWAYS_ON },
+	{ "a3ir",	0x180, 0, R8A7795_PD_A3IR,	R8A7795_PD_ALWAYS_ON,
+	  (PD_NO_CR | PD_ON_ONCE) },
 };
 
 const struct rcar_sysc_info r8a7795_sysc_info __initconst = {

drivers/soc/renesas/r8a7796-sysc.c

@@ -33,13 +33,18 @@ static const struct rcar_sysc_area r8a7796_areas[] __initconst = {
 	  PD_CPU_NOCR },
 	{ "ca53-cpu3",	0x200, 3, R8A7796_PD_CA53_CPU3,	R8A7796_PD_CA53_SCU,
 	  PD_CPU_NOCR },
-	{ "cr7",	0x240, 0, R8A7796_PD_CR7,	R8A7796_PD_ALWAYS_ON },
-	{ "a3vc",	0x380, 0, R8A7796_PD_A3VC,	R8A7796_PD_ALWAYS_ON },
-	{ "a2vc0",	0x3c0, 0, R8A7796_PD_A2VC0,	R8A7796_PD_A3VC },
-	{ "a2vc1",	0x3c0, 1, R8A7796_PD_A2VC1,	R8A7796_PD_A3VC },
+	{ "cr7",	0x240, 0, R8A7796_PD_CR7,	R8A7796_PD_ALWAYS_ON,
+	  (PD_NO_CR | PD_ON_ONCE) },
+	{ "a3vc",	0x380, 0, R8A7796_PD_A3VC,	R8A7796_PD_ALWAYS_ON,
+	  (PD_NO_CR | PD_ON_ONCE) },
+	{ "a2vc0",	0x3c0, 0, R8A7796_PD_A2VC0,	R8A7796_PD_A3VC,
+	  (PD_NO_CR | PD_ON_ONCE) },
+	{ "a2vc1",	0x3c0, 1, R8A7796_PD_A2VC1,	R8A7796_PD_A3VC,
+	  (PD_NO_CR | PD_ON_ONCE) },
 	{ "3dg-a",	0x100, 0, R8A7796_PD_3DG_A,	R8A7796_PD_ALWAYS_ON },
 	{ "3dg-b",	0x100, 1, R8A7796_PD_3DG_B,	R8A7796_PD_3DG_A },
-	{ "a3ir",	0x180, 0, R8A7796_PD_A3IR,	R8A7796_PD_ALWAYS_ON },
+	{ "a3ir",	0x180, 0, R8A7796_PD_A3IR,	R8A7796_PD_ALWAYS_ON,
+	  (PD_NO_CR | PD_ON_ONCE) },
 };
 
 const struct rcar_sysc_info r8a7796_sysc_info __initconst = {

drivers/soc/renesas/rcar-sysc.c

@@ -17,6 +17,7 @@
 #include <linux/pm_domain.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
+#include <linux/syscore_ops.h>
 #include <linux/io.h>
 #include <linux/soc/renesas/rcar-sysc.h>
 
@@ -328,6 +329,34 @@ struct rcar_pm_domains {
 	struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
 };
 
+struct rcar_sysc_pd *rcar_domains[RCAR_PD_ALWAYS_ON + 1];
+
+static void rcar_power_on_force(void)
+{
+	int i;
+
+	for (i = 0; i < RCAR_PD_ALWAYS_ON; i++) {
+		struct rcar_sysc_pd *pd = rcar_domains[i];
+
+		if (!pd)
+			continue;
+
+		if (!(pd->flags & PD_ON_ONCE))
+			continue;
+
+		if (!rcar_sysc_power_is_off(&pd->ch))
+			continue;
+
+		rcar_sysc_power_up(&pd->ch);
+	}
+}
+
+#ifdef CONFIG_PM_SLEEP
+static struct syscore_ops rcar_sysc_syscore_ops = {
+	.resume = rcar_power_on_force,
+};
+#endif
+
 static int __init rcar_sysc_pd_init(void)
 {
 	const struct rcar_sysc_info *info;
@@ -410,8 +439,14 @@ static int __init rcar_sysc_pd_init(void)
 					       &pd->genpd);
 
 		domains->domains[area->isr_bit] = &pd->genpd;
+
+		rcar_domains[i] = pd;
 	}
 
+#if IS_ENABLED(CONFIG_ARCH_R8A7795) || IS_ENABLED(CONFIG_ARCH_R8A7796)
+	rcar_power_on_force();
+#endif
+
 	error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
 
 out_put:
@@ -420,6 +455,17 @@ static int __init rcar_sysc_pd_init(void)
 }
 early_initcall(rcar_sysc_pd_init);
 
+#if IS_ENABLED(CONFIG_ARCH_R8A7795) || IS_ENABLED(CONFIG_ARCH_R8A7796)
+static int __init rcar_sysc_pd_init2(void)
+{
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&rcar_sysc_syscore_ops);
+#endif
+	return 0;
+}
+postcore_initcall(rcar_sysc_pd_init2);
+#endif
+
 void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
 {
 	u32 syscimr;

drivers/soc/renesas/rcar-sysc.h

@@ -21,6 +21,7 @@
 #define PD_NO_CR	BIT(2)	/* Area lacks PWR{ON,OFF}CR registers */
 
 #define PD_BUSY		BIT(3)	/* Busy, for internal use only */
+#define PD_ON_ONCE	BIT(4)  /* Turned on once at boot */
 
 #define PD_CPU_CR	PD_CPU		  /* CPU area has CR (R-Car H1) */
 #define PD_CPU_NOCR	PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */