vsp1 and rcar-du from BSP v4.9/3.5.8

drivers/gpu/drm/bridge/dw-hdmi.c

@@ -224,7 +224,11 @@ static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 
 	/* Set Standard Mode speed (determined to be 100KHz on iMX6) */
-	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
+	if (hdmi->dev_type == RCAR_HDMI)
+		hdmi_modb(hdmi, 0x00, HDMI_I2CM_DIV_FAST_STD_MODE_MASK,
+			  HDMI_I2CM_DIV);
+	else
+		hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
 
 	/* Set done, not acknowledged and arbitration interrupt polarities */
 	hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
@@ -720,8 +724,11 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi)
 
 	/* Configure the CSC registers */
 	hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
-	hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
-		  HDMI_CSC_SCALE);
+
+	if (hdmi->dev_type != RCAR_HDMI)
+		hdmi_modb(hdmi, color_depth,
+			  HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
+			  HDMI_CSC_SCALE);
 
 	dw_hdmi_update_csc_coeffs(hdmi);
 }
@@ -771,12 +778,14 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 	}
 
 	/* set the packetizer registers */
-	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
-		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
-		((hdmi_data->pix_repet_factor <<
-		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
-		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
-	hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
+	if (hdmi->dev_type != RCAR_HDMI) {
+		val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
+			HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
+			((hdmi_data->pix_repet_factor <<
+			HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
+			HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
+		hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
+	}
 
 	hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 		  HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
@@ -790,14 +799,20 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 			  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 	}
 
-	hdmi_modb(hdmi, vp_conf,
-		  HDMI_VP_CONF_PR_EN_MASK |
-		  HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
+	if (hdmi->dev_type == RCAR_HDMI)
+		hdmi_modb(hdmi, vp_conf,
+			  HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
+	else
+		hdmi_modb(hdmi, vp_conf,
+			  HDMI_VP_CONF_PR_EN_MASK |
+			  HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 
 	hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 		  HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 
-	hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
+	if (hdmi->dev_type != RCAR_HDMI) {
+		hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
+	}
 
 	if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 		vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
@@ -815,9 +830,15 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 		return;
 	}
 
-	hdmi_modb(hdmi, vp_conf,
-		  HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
-		  HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
+	if (hdmi->dev_type == RCAR_HDMI)
+		hdmi_modb(hdmi, vp_conf,
+			  HDMI_VP_CONF_BYPASS_EN_MASK |
+			  HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
+	else
+		hdmi_modb(hdmi, vp_conf,
+			  HDMI_VP_CONF_BYPASS_EN_MASK |
+			  HDMI_VP_CONF_PP_EN_ENMASK |
+			  HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 
 	hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 			HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
@@ -826,38 +847,58 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 
 	hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 		  HDMI_VP_CONF);
+
+	/* ycc422_stuffing bit only in R-Car */
+	if (hdmi->dev_type == RCAR_HDMI)
+		hdmi_writeb(hdmi, HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
+			    HDMI_VP_STUFF);
 }
 
 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 				       unsigned char bit)
 {
+	if (hdmi->dev_type == RCAR_HDMI)
+		return;
+
 	hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 		  HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 }
 
 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 					unsigned char bit)
 {
+	if (hdmi->dev_type == RCAR_HDMI)
+		return;
+
 	hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 		  HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 }
 
 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 				       unsigned char bit)
 {
+	if (hdmi->dev_type == RCAR_HDMI)
+		return;
+
 	hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 		  HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 }
 
 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 				     unsigned char bit)
 {
+	if (hdmi->dev_type == RCAR_HDMI)
+		return;
+
 	hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 }
 
 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 				      unsigned char bit)
 {
+	if (hdmi->dev_type == RCAR_HDMI)
+		return;
+
 	hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 }
 
@@ -903,13 +944,19 @@ static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 
 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
 {
+	if (hdmi->dev_type == RCAR_HDMI)
+		return;
+
 	hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
 			 HDMI_PHY_CONF0_PDZ_OFFSET,
 			 HDMI_PHY_CONF0_PDZ_MASK);
 }
 
 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 {
+	if (hdmi->dev_type == RCAR_HDMI)
+		return;
+
 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 			 HDMI_PHY_CONF0_ENTMDS_OFFSET,
 			 HDMI_PHY_CONF0_ENTMDS_MASK);
@@ -1035,7 +1082,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 
-	hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
+	if (hdmi->dev_type != RCAR_HDMI)
+		hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT,
+			    HDMI_MC_HEACPHY_RST);
 
 	hdmi_phy_test_clear(hdmi, 1);
 	hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
@@ -1538,20 +1587,20 @@ static void initialize_hdmi_rcar_ih_mutes(struct dw_hdmi *hdmi)
 	hdmi_writeb(hdmi, 0x0c, HDMI_PHY_I2CM_INT_ADDR);
 	hdmi_writeb(hdmi, 0xcc, HDMI_PHY_I2CM_CTLINT_ADDR);
 	hdmi_writeb(hdmi, 0x0c, HDMI_AUD_INT);
-	hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
+	hdmi_writeb(hdmi, 0xdf, HDMI_A_APIINTMSK);
 	hdmi_writeb(hdmi, 0x7f, HDMI_CEC_MASK);
 	hdmi_writeb(hdmi, 0x44, HDMI_I2CM_INT);
 	hdmi_writeb(hdmi, 0x44, HDMI_I2CM_CTLINT);
 
 	/* Disable interrupts in the IH_MUTE_* registers */
-	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
+	hdmi_writeb(hdmi, 0xc7, HDMI_IH_MUTE_FC_STAT0);
 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
 	hdmi_writeb(hdmi, 0x03, HDMI_IH_MUTE_FC_STAT2);
 	hdmi_writeb(hdmi, 0x1f, HDMI_IH_MUTE_AS_STAT0);
 	hdmi_writeb(hdmi, 0x3f, HDMI_IH_MUTE_PHY_STAT0);
-	hdmi_writeb(hdmi, 0x0f, HDMI_IH_MUTE_I2CM_STAT0);
+	hdmi_writeb(hdmi, 0x03, HDMI_IH_MUTE_I2CM_STAT0);
 	hdmi_writeb(hdmi, 0x7f, HDMI_IH_MUTE_CEC_STAT0);
-	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
+	hdmi_writeb(hdmi, 0x0f, HDMI_IH_MUTE_VP_STAT0);
 	hdmi_writeb(hdmi, 0x03, HDMI_IH_MUTE_I2CMPHY_STAT0);
 
 	/* Enable top level interrupt bits in HDMI block */
@@ -1685,6 +1734,36 @@ static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
 	mutex_unlock(&hdmi->mutex);
 }
 
+/*
+ * This function controls clocks of dw_hdmi through drm_bridge
+ * at system suspend/resume.
+ * Arguments:
+ *  bridge: drm_bridge that contains dw_hdmi.
+ *  flag: controlled flag.
+ *		0: is used when suspend.
+ *		1: is used when resume.
+ */
+void dw_hdmi_s2r_ctrl(struct drm_bridge *bridge, int flag)
+{
+	struct dw_hdmi *hdmi = bridge->driver_private;
+
+	if (hdmi->dev_type != RCAR_HDMI)
+		return;
+
+	if (flag) { /* enable clk */
+		if (hdmi->isfr_clk)
+			clk_prepare_enable(hdmi->isfr_clk);
+		if (hdmi->iahb_clk)
+			clk_prepare_enable(hdmi->iahb_clk);
+	} else { /* disable clk */
+		if (hdmi->isfr_clk)
+			clk_disable_unprepare(hdmi->isfr_clk);
+		if (hdmi->iahb_clk)
+			clk_disable_unprepare(hdmi->iahb_clk);
+	}
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_s2r_ctrl);
+
 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
 {
 	struct dw_hdmi *hdmi = bridge->driver_private;
@@ -1693,12 +1772,6 @@ static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
 	hdmi->disabled = true;
 	dw_hdmi_update_power(hdmi);
 	dw_hdmi_update_phy_mask(hdmi);
-
-	if (hdmi->dev_type == RCAR_HDMI) {
-		hdmi_writeb(hdmi, 0x3f, HDMI_IH_MUTE_PHY_STAT0);
-		hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE,
-					 HDMI_PHY_POL0);
-	}
 	mutex_unlock(&hdmi->mutex);
 }
 

drivers/gpu/drm/bridge/dw-hdmi.h

@@ -1059,6 +1059,9 @@ enum {
 	HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
 	HDMI_I2CM_CTLINT_ARB_POL = 0x8,
 	HDMI_I2CM_CTLINT_ARB_MASK = 0x4,
+
+/* I2CM_DIV field values */
+	HDMI_I2CM_DIV_FAST_STD_MODE_MASK = 0x08,
 };
 
 #endif /* __DW_HDMI_H__ */

drivers/gpu/drm/drm_atomic_helper.c

@@ -1144,6 +1144,36 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device *dev,
 }
 EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks);
 
+/**
+ * drm_atomic_helper_wait_for_flip_done - wait for all page flips to be done
+ * @state: atomic state object
+ *
+ * Helper to, after atomic commit, wait for page flips on all effected
+ * crtcs (ie. before cleaning up old framebuffers using
+ * drm_atomic_helper_cleanup_planes()).
+ */
+void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev,
+					  struct drm_atomic_state *state)
+{
+	struct drm_crtc_state *crtc_state;
+	struct drm_crtc *crtc;
+	int i;
+
+	for_each_crtc_in_state(state, crtc, crtc_state, i) {
+		struct drm_crtc_commit *commit = state->crtcs[i].commit;
+		int ret;
+
+		if (!commit)
+			continue;
+
+		ret = wait_for_completion_timeout(&commit->flip_done, 10 * HZ);
+		if (ret == 0)
+			DRM_ERROR("[CRTC:%d:%s] flip_done timed out\n",
+				  crtc->base.id, crtc->name);
+	}
+}
+EXPORT_SYMBOL(drm_atomic_helper_wait_for_flip_done);
+
 /**
  * drm_atomic_helper_commit_tail - commit atomic update to hardware
  * @state: new modeset state to be committed