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LTX-2.5 optimization: integrate faster AITER NA3D flash attention for diffusion decoder - #773
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The PR lint job checks whole changed files, and ltx.py was not ruff-clean on main. Move the cache import into the top import block and apply ruff-format (v0.11.13, as pinned in .pre-commit-config.yaml). No behavior change (AST identical apart from the moved import).
- Resolve the aiter na3d_flash import and check for a gfx942/gfx950 device when the processor is constructed, so the runner falls back to tiled SDPA instead of failing on the first decode call. - Route grids outside the kernel's asserted domain (bf16, W >= 16, KW <= 33, KW > 17 needs W >= 32, power-of-two head_dim) to the tiled SDPA processor; decoder tiling can produce remnant tiles as narrow as the kernel. - Runner: drop the triton import gate, catch only ImportError and RuntimeError, and log why the SDPA fallback was chosen. - Tests: CPU contract for the ImportError fallback; ROCm parity against the tiled SDPA processor for the LTX-2.5 kernel sizes, plus the narrow-tile path.
jjuvonen-amd
marked this pull request as ready for review
October 5, 2026 11:29
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Hi, sorry the review took a while. This looks good to me! Can you fix the conflicts in |
# Conflicts: # xfuser/model_executor/models/runner_models/ltx.py
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Thanks @avjves, the conflicts are now resolved and this merges cleanly. |
avjves
approved these changes
Oct 9, 2026
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Summary
Adds an LTX-2.5 diffusion-decoder attention processor (
LTX2VideoVaeMfmaAttnProcessor) that uses AITER's Triton 3D neighborhood flash attention (aiter.ops.triton.attention.na3d_flash, added in ROCm/aiter#5230, now merged), with a fused QKV projection.The decoder now picks its attention processor in this order: NATTEN -> AITER flash-NA3D (ROCm gfx942/gfx950) -> tiled PyTorch SDPA.
na3d_flashraisesImportError, and an unsupported device raisesRuntimeError. The runner catches both and falls back to tiled SDPA, logging the reason.W < 16,KW > 33,KW > 17withW < 32, or a head_dim that isn't a power of two ≥ 16) go to the tiled SDPA processor. Decoder tiling can leave edge tiles as narrow as the kernel size, so this case does occur.runner_models/ltx.pyis reformatted with ruff in a separate, style-only commit, because the lint job checks whole changed files and this file was not ruff-clean on main. It moves one import to fix E402; there is no behavior change.Requires an AITER build that includes ROCm/aiter#5230. Without it, the decoder falls back to tiled SDPA as before.
Validation
Automated lint, formatting, CPU unit, and CPU integration checks run in PR CI. They do not cover accelerator behavior.
New tests:
tests/unit/model_executor/layers/ltx2/test_na3d_mfma_flash.py: constructing the processor raisesImportErrorwhen AITER lacksna3d_flash. The runner's fallback depends on this.tests/integration/accelerator/model_executor/layers/test_ltx2_na3d_flash.py(rocm):Environment: 8x AMD Instinct MI350X (gfx950), ROCm 7.14, PyTorch 2.9.1, Triton 3.5.1, AITER main @
7bfe279de(includes #5230), diffusers 0.41.0.dev0 @9f7aee482.pre-commit run --from-ref <base> --to-ref HEADpython -m pytest tests/unit -m "not accelerator"python -m pytest tests/integration/cpu -m "not accelerator"The 2 CPU-integration skips are environmental: one because real GPUs are present, one because the installed diffusers is not a final release.
Accelerator tests
Hardware, environment, command, and result:
python -m pytest -m "accelerator and not nvidia and not multi_gpu"-> 94 passed, 2 skipped, 2 xfailed, 922 deselectedpython -m pytest -m "accelerator and multi_gpu and not nvidia"-> 4 passed, 1 skipped, 1015 deselectedEnd-to-end tests
Model, command, result, and any relevant performance or quality comparison:
Lightricks/LTX-2.5-Diffusers (distilled), i2v, 1536x1024, 121 frames, 8 steps, seed 42, MI350X:
The tiled SDPA baseline ran on the same branch with AITER's
na3d_flashhidden, which forces the runner's fallback. Decode time is measured arounddecode_pipe(...)with a CUDA sync on each side, averaged over 2 iterations after warm-up (slowest rank on 8 GPUs).Output quality: I visually compared frames from the 1-GPU and 8-GPU outputs against earlier reference videos. They show no tile seams or artifacts (videos attached below).
Tiled SDPA fallback
mi350_ltx_2_5_distilled_video_u8r1_tc_True_1536x1024_i2v_aiter-RMSNorm-pvae.mp4
With AITER na3d_flash kernel
ltx_2_5_distilled_video_u1r1_tc_True_1536x1024_i2v_0_triton_na_mi355x.mp4
Notes