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CTC & CPU Speed
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- Revamped CTC detection algorithm hoping to handle problem XRBR is having
- Fixed typo in dynamic CPU speed test that caused it to not be properly recorded/reported (credit XRBR)
- Allow use of DEL/RUBOUT keys as backspace in ROM Loader and Debug Monitor
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wwarthen committed Mar 23, 2023
1 parent 8aebaab commit 98a33b8
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Showing 6 changed files with 44 additions and 38 deletions.
61 changes: 30 additions & 31 deletions Source/HBIOS/ctc.asm
Original file line number Diff line number Diff line change
Expand Up @@ -147,18 +147,16 @@ CTCTIVT .EQU INT_CTC0A + CTCTIMCH
;==================================================================================================
;
CTC_PREINIT:
; BLINDLY RESET THE CTC ASSUMING IT IS THERE
LD A,CTC_DEFCFG
OUT (CTCBASE),A
OUT (CTCBASE+1),A
OUT (CTCBASE+2),A
OUT (CTCBASE+3),A
;
CALL CTC_DETECT ; DO WE HAVE ONE?
LD (CTC_EXIST),A ; SAVE IT
RET NZ ; ABORT IF NONE
;
; RESET ALL CTC CHANNELS
LD B,4 ; 4 CHANNELS
LD C,CTCBASE ; FIRST CHANNEL PORT
CTC_PREINIT1:
LD A,CTC_DEFCFG ; CTC DEFAULT CONFIG
OUT (C),A ; CTC COMMAND
INC C ; NEXT CHANNEL PORT
DJNZ CTC_PREINIT1
;
#IF (CTCTIMER & (INTMODE == 2))
; SETUP TIMER INTERRUPT IVT SLOT
Expand Down Expand Up @@ -258,32 +256,33 @@ CTC_PRTCFG1:
RET
;
;==================================================================================================
; DETECT CTC BY CHECKING REGISTER CAN BE WRITTEN AND READ, AND THEN BY SETTING UP ONE CHANNEL IN
; TIMER MODE AND CHECKING IT IS COUNTING DOWN.
; DETECT CTC BY PROGRAMMING THE FIRST CHANNEL TO COUNT IN TIMER
; MODE (BASED ON CPU CLOCK). THEN CHECK IF COUNTER IS ACTUALLY
; RUNNING.
;==================================================================================================
;
CTC_DETECT:
LD A,CTC_TIM256CFG
OUT (CTCBASE),A
XOR A
OUT (CTCBASE),A
; CTC SHOULD NOW BE RUNNING WITH TIME CONSTANT 0
LD A,CTC_TIM256CFG ; RESET
OUT (CTCBASE),A
IN A,(CTCBASE) ; SHOULD READ 0 NOW
CP 0
JR NZ,CTC_NO
LD A,CTC_TIM16CFG ; RESET & SETUP TIMER MODE
OUT (CTCBASE),A ; SEND TO CTC
LD A,$FF ; TIME CONSTANT $FF
OUT (CTCBASE),A
IN A,(CTCBASE) ; SHOULD NOT BE 0 NOW
CP 0
JR Z,CTC_NO
XOR A
RET
OUT (CTCBASE),A ; SEND CONSTANT & START CTR
NOP ; BRIEF DELAY
IN A,(CTCBASE) ; READ COUNTER
LD C,A ; SAVE VALUE
CALL DLY8 ; WAIT A BIT
IN A,(CTCBASE) ; READ COUNTER AGAIN
PUSH AF ; SAVE RESULT
LD A,CTC_DEFCFG ; DEFAULT CHANNEL CFG
OUT (CTCBASE),A ; RESTORE TO DEFAULTS
POP AF ; GET RESULT BACK
CP C ; COMPARE TO PREVIOUS
JR Z,CTC_NO ; IF SAME, FAIL
XOR A ; SIGNAL SUCCESS
RET ; AND DONE
CTC_NO:
OR $FF
RET
;
OR $FF ; SIGNAL FAILURE
RET ; AND DONE
;
; CTC DRIVER DATA STORAGE
;
CTC_EXIST .DB $FF
CTC_EXIST .DB $FF ; SET TO ZERO IF EXISTS
3 changes: 3 additions & 0 deletions Source/HBIOS/dbgmon.asm
Original file line number Diff line number Diff line change
Expand Up @@ -878,6 +878,8 @@ GETLNLOP:
JR Z,GETLNDONE ; YES, EXIT
CP CHR_BS ; IS <BS>?
JR Z,GETLNBS ; IF SO, HANDLE IT
CP CHR_DEL ; IS <DEL>?
JR Z,GETLNBS ; IF SO, HANDLE AS <BS>
CP ' ' ; UNEXPECTED CONTROL CHAR?
JR C,GETLNLOP ; IF SO, IGNORE IT AND GET NEXT
LD B,A ; SAVE CHAR IN B FOR NOW
Expand Down Expand Up @@ -1854,6 +1856,7 @@ CHR_CR .EQU 0DH
CHR_LF .EQU 0AH
CHR_BS .EQU 08H
CHR_ESC .EQU 1BH
CHR_DEL .EQU 7FH
;
;__________________________________________________________________________________________________
;
Expand Down
11 changes: 6 additions & 5 deletions Source/HBIOS/hbios.asm
Original file line number Diff line number Diff line change
Expand Up @@ -1898,17 +1898,17 @@ HB_CPU1:
;
; INIT OSCILLATOR SPEED FROM CONFIG
;
LD HL,CPUOSC / 1000
LD (HB_CPUOSC),HL
LD HL,CPUOSC / 1000 ; OSC SPD IN KHZ
LD (HB_CPUOSC),HL ; INIT HB_CPUOSC DEFAULT
;
; ATTEMPT DYNAMIC CPU SPEED DERIVATION
; NOTE THAT FOR PLATFORMS WITH SOFTWARE SELECTABLE CPU SPEED,
; THIS IS BEING DONE WITH THE CPU SPEED SET TO THE LOWEST
; POSSIBLE SETTING. THE FINAL CPU SPEED WILL BE ADJUSTED
; LATER.
;
CALL HB_CPUSPD ; CPU SPEED DETECTION
JR NZ,HB_CPUSPD2 ; SKIP IF FAILED
CALL HB_CPUSPD ; DYNAMIC CPU SPEED DETECTION
JR NZ,HB_CPUSPD2 ; SKIP AHEAD IF FAILED
;
; RECORD THE UPDATED CPU OSCILLATOR SPEED
;
Expand All @@ -1917,8 +1917,9 @@ HB_CPU1:
; SO RECORD DOUBLE THE MEASURED VALUE
SLA L
RL H
LD (HB_CPUOSC),HL
#ENDIF
;
LD (HB_CPUOSC),HL ; RECORD MEASURED SPEED
;
HB_CPUSPD2:
;
Expand Down
3 changes: 3 additions & 0 deletions Source/HBIOS/romldr.asm
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,7 @@ bel .equ 7 ; ASCII bell
bs .equ 8 ; ASCII backspace
lf .equ 10 ; ASCII linefeed
cr .equ 13 ; ASCII carriage return
del .equ 127 ; ASCII del/rubout
;
cmdbuf .equ $80 ; cmd buf is in second half of page zero
cmdmax .equ 60 ; max cmd len (arbitrary), must be < bufsiz
Expand Down Expand Up @@ -1281,6 +1282,8 @@ rdln_nxt:
call cin ; get a character
cp bs ; backspace?
jr z,rdln_bs ; handle it if so
cp del ; del/rubout?
jr z,rdln_bs ; handle as backspace
cp cr ; return?
jr z,rdln_cr ; handle it if so
;
Expand Down
2 changes: 1 addition & 1 deletion Source/ver.inc
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
#DEFINE RMN 2
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.2.1-dev.1"
#DEFINE BIOSVER "3.2.1-dev.2"
#define rmj RMJ
#define rmn RMN
#define rup RUP
Expand Down
2 changes: 1 addition & 1 deletion Source/ver.lib
Original file line number Diff line number Diff line change
Expand Up @@ -3,5 +3,5 @@ rmn equ 2
rup equ 1
rtp equ 0
biosver macro
db "3.2.1-dev.1"
db "3.2.1-dev.2"
endm

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