Merge pull request #9 from dhil/wasmfx

Weekly merge
wasmfx · Sep 22, 2023 · aeaa010 · aeaa010
2 parents 031d2f1 + 3c16048
commit aeaa010
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diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -210,15 +210,15 @@ is-terminal = "0.4.0"
 wit-bindgen = { version = "0.11.0", default-features = false }
 
 # wasm-tools family:
-wasmparser = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.40" }
-wat = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.40" }
-wast = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.40" }
-wasmprinter = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.40" }
-wasm-encoder = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.40" }
-wasm-smith = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.40" }
-wasm-mutate = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.40" }
-wit-parser = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.40" }
-wit-component = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.40" }
+wasmparser    = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.42.hotfix" }
+wat           = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.42.hotfix" }
+wast          = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.42.hotfix" }
+wasmprinter   = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.42.hotfix" }
+wasm-encoder  = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.42.hotfix" }
+wasm-smith    = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.42.hotfix" }
+wasm-mutate   = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.42.hotfix" }
+wit-parser    = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.42.hotfix" }
+wit-component = { git = "https://github.com/wasmfx/wasmfx-tools", tag = "wasmfx-tools-1.0.42.hotfix" }
 
 # Non-Bytecode Alliance maintained dependencies:
 # --------------------------

diff --git a/RELEASES.md b/RELEASES.md
@@ -12,7 +12,7 @@ Unreleased.
 
 ## 13.0.0
 
-Unreleased.
+Released 2023-09-20
 
 ### Added
 

diff --git a/cranelift/codegen/src/binemit/mod.rs b/cranelift/codegen/src/binemit/mod.rs
@@ -92,6 +92,18 @@ pub enum Reloc {
     /// jalr ra, ra, 0
     RiscvCall,
 
+    /// RISC-V TLS GD: High 20 bits of 32-bit PC-relative TLS GD GOT reference,
+    ///
+    /// This is the `R_RISCV_TLS_GD_HI20` relocation from the RISC-V ELF psABI document.
+    /// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#global-dynamic
+    RiscvTlsGdHi20,
+
+    /// Low 12 bits of a 32-bit PC-relative relocation (I-Type instruction)
+    ///
+    /// This is the `R_RISCV_PCREL_LO12_I` relocation from the RISC-V ELF psABI document.
+    /// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses
+    RiscvPCRelLo12I,
+
     /// s390x TLS GD64 - 64-bit offset of tls_index for GD symbol in GOT
     S390xTlsGd64,
     /// s390x TLS GDCall - marker to enable optimization of TLS calls
@@ -114,7 +126,8 @@ impl fmt::Display for Reloc {
             Self::X86SecRel => write!(f, "SecRel"),
             Self::Arm32Call | Self::Arm64Call => write!(f, "Call"),
             Self::RiscvCall => write!(f, "RiscvCall"),
-
+            Self::RiscvTlsGdHi20 => write!(f, "RiscvTlsGdHi20"),
+            Self::RiscvPCRelLo12I => write!(f, "RiscvPCRelLo12I"),
             Self::ElfX86_64TlsGd => write!(f, "ElfX86_64TlsGd"),
             Self::MachOX86_64Tlv => write!(f, "MachOX86_64Tlv"),
             Self::MachOAarch64TlsAdrPage21 => write!(f, "MachOAarch64TlsAdrPage21"),

diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
@@ -3174,7 +3174,7 @@ impl MachInstEmit for Inst {
                 // Note: this is not `Inst::Jump { .. }.emit(..)` because we
                 // have different metadata in this case: we don't have a label
                 // for the target, but rather a function relocation.
-                sink.add_reloc(Reloc::Arm64Call, callee, 0);
+                sink.add_reloc(Reloc::Arm64Call, &**callee, 0);
                 sink.put4(enc_jump26(0b000101, 0));
                 sink.add_call_site(ir::Opcode::ReturnCall);
 
@@ -3382,12 +3382,12 @@ impl MachInstEmit for Inst {
                     //   ldr     rd, [rd, :got_lo12:X]
 
                     // adrp rd, symbol
-                    sink.add_reloc(Reloc::Aarch64AdrGotPage21, name, 0);
+                    sink.add_reloc(Reloc::Aarch64AdrGotPage21, &**name, 0);
                     let inst = Inst::Adrp { rd, off: 0 };
                     inst.emit(&[], sink, emit_info, state);
 
                     // ldr rd, [rd, :got_lo12:X]
-                    sink.add_reloc(Reloc::Aarch64Ld64GotLo12Nc, name, 0);
+                    sink.add_reloc(Reloc::Aarch64Ld64GotLo12Nc, &**name, 0);
                     let inst = Inst::ULoad64 {
                         rd,
                         mem: AMode::reg(rd.to_reg()),
@@ -3415,7 +3415,7 @@ impl MachInstEmit for Inst {
                         dest: BranchTarget::ResolvedOffset(12),
                     };
                     inst.emit(&[], sink, emit_info, state);
-                    sink.add_reloc(Reloc::Abs8, name, offset);
+                    sink.add_reloc(Reloc::Abs8, &**name, offset);
                     sink.put8(0);
                 }
             }

diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs
@@ -290,7 +290,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
 
     fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Inst> {
         let mut insts = SmallVec::new();
-        insts.push(Inst::TrapIfC {
+        insts.push(Inst::TrapIf {
             cc: IntCC::UnsignedLessThan,
             rs1: stack_reg(),
             rs2: limit_reg,

diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -122,12 +122,8 @@
       (callee Reg)
       (info BoxReturnCallInfo))
 
+    ;; Emits a trap with the given trap code if the comparison succeeds
     (TrapIf
-      (test Reg)
-      (trap_code TrapCode))
-
-    ;; use a simple compare to decide to cause trap or not.
-    (TrapIfC
       (rs1 Reg)
       (rs2 Reg)
       (cc IntCC)
@@ -148,6 +144,11 @@
       (name BoxExternalName)
       (offset i64))
 
+    ;; Load a TLS symbol address
+    (ElfTlsGetAddr
+      (rd WritableReg)
+      (name BoxExternalName))
+
     ;; Load address referenced by `mem` into `rd`.
     (LoadAddr
       (rd WritableReg)
@@ -714,6 +715,9 @@
   (CAdd)
   (CJr)
   (CJalr)
+  ;; c.ebreak technically isn't a CR format instruction, but it's encoding
+  ;; lines up with this format.
+  (CEbreak)
 ))
 
 ;; Opcodes for the CA compressed instruction format
@@ -731,6 +735,19 @@
   (CJ)
 ))
 
+;; Opcodes for the CI compressed instruction format
+(type CiOp (enum
+  (CAddi)
+  (CAddiw)
+  (CAddi16sp)
+  (CSlli)
+))
+
+;; Opcodes for the CIW compressed instruction format
+(type CiwOp (enum
+  (CAddi4spn)
+))
+
 
 (type CsrRegOP (enum
   ;; Atomic Read/Write CSR
@@ -2625,6 +2642,12 @@
 (decl load_ext_name (ExternalName i64) Reg)
 (extern constructor load_ext_name load_ext_name)
 
+(decl elf_tls_get_addr (ExternalName) Reg)
+(rule (elf_tls_get_addr name)
+      (let ((dst WritableReg (temp_writable_reg $I64))
+            (_ Unit (emit (MInst.ElfTlsGetAddr dst name))))
+        dst))
+
 (decl int_convert_2_float_op (Type bool Type) FpuOPRR)
 (extern constructor int_convert_2_float_op int_convert_2_float_op)
 
@@ -2866,36 +2889,39 @@
   (gen_select_reg (IntCC.SignedGreaterThan) x y x y))
 
 
-(decl gen_trapif (XReg TrapCode) InstOutput)
-(rule
-  (gen_trapif test trap_code)
-  (side_effect (SideEffectNoResult.Inst (MInst.TrapIf test trap_code))))
+;; Builds an instruction sequence that traps if the comparision succeeds.
+(decl gen_trapif (IntCC XReg XReg TrapCode) InstOutput)
+(rule (gen_trapif cc a b trap_code)
+  (side_effect (SideEffectNoResult.Inst (MInst.TrapIf a b cc trap_code))))
+
+;; Builds an instruction sequence that traps if the input is non-zero.
+(decl gen_trapnz (XReg TrapCode) InstOutput)
+(rule (gen_trapnz test trap_code)
+  (gen_trapif (IntCC.NotEqual) test (zero_reg) trap_code))
+
+;; Builds an instruction sequence that traps if the input is zero.
+(decl gen_trapz (XReg TrapCode) InstOutput)
+(rule (gen_trapz test trap_code)
+  (gen_trapif (IntCC.Equal) test (zero_reg) trap_code))
 
-(decl gen_trapifc (IntCC XReg XReg TrapCode) InstOutput)
-(rule
-  (gen_trapifc cc a b trap_code)
-  (side_effect (SideEffectNoResult.Inst (MInst.TrapIfC a b cc trap_code))))
 
 (decl shift_int_to_most_significant (XReg Type) XReg)
 (extern constructor shift_int_to_most_significant shift_int_to_most_significant)
 
 ;;; generate div overflow.
 (decl gen_div_overflow (XReg XReg Type) InstOutput)
-(rule
-  (gen_div_overflow rs1 rs2 ty)
-  (let
-    ((r_const_neg_1 XReg (imm $I64 (i64_as_u64 -1)))
-      (r_const_min XReg (rv_slli (imm $I64 1) (imm12_const 63)))
-      (tmp_rs1 XReg (shift_int_to_most_significant rs1 ty))
-      (t1 XReg (gen_icmp (IntCC.Equal) r_const_neg_1 rs2 ty))
-      (t2 XReg (gen_icmp (IntCC.Equal) r_const_min tmp_rs1 ty))
-      (test XReg (rv_and t1 t2)))
-    (gen_trapif test (TrapCode.IntegerOverflow))))
+(rule (gen_div_overflow rs1 rs2 ty)
+  (let ((r_const_neg_1 XReg (imm $I64 (i64_as_u64 -1)))
+        (r_const_min XReg (rv_slli (imm $I64 1) (imm12_const 63)))
+        (tmp_rs1 XReg (shift_int_to_most_significant rs1 ty))
+        (t1 XReg (gen_icmp (IntCC.Equal) r_const_neg_1 rs2 ty))
+        (t2 XReg (gen_icmp (IntCC.Equal) r_const_min tmp_rs1 ty))
+        (test XReg (rv_and t1 t2)))
+    (gen_trapnz test (TrapCode.IntegerOverflow))))
 
 (decl gen_div_by_zero (XReg) InstOutput)
-(rule
-  (gen_div_by_zero r)
-  (gen_trapifc (IntCC.Equal) (zero_reg) r (TrapCode.IntegerDivisionByZero)))
+(rule (gen_div_by_zero r)
+  (gen_trapz r (TrapCode.IntegerDivisionByZero)))
 
 ;;;; Helpers for Emitting Calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 

diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs
@@ -6,7 +6,10 @@ use super::*;
 use crate::ir::condcodes::CondCode;
 
 use crate::isa::riscv64::inst::{reg_name, reg_to_gpr_num};
-use crate::isa::riscv64::lower::isle::generated_code::{COpcodeSpace, CaOp, CjOp, CrOp};
+
+use crate::isa::riscv64::lower::isle::generated_code::{
+    COpcodeSpace, CaOp, CiOp, CiwOp, CjOp, CrOp,
+};
 use crate::machinst::isle::WritableReg;
 
 use std::fmt::{Display, Formatter, Result};
@@ -1916,14 +1919,14 @@ impl CrOp {
         match self {
             // `c.jr` has the same op/funct4 as C.MV, but RS2 is 0, which is illegal for mv.
             CrOp::CMv | CrOp::CJr => 0b1000,
-            CrOp::CAdd | CrOp::CJalr => 0b1001,
+            CrOp::CAdd | CrOp::CJalr | CrOp::CEbreak => 0b1001,
         }
     }
 
     pub fn op(&self) -> COpcodeSpace {
         // https://five-embeddev.com/riscv-isa-manual/latest/rvc-opcode-map.html#rvcopcodemap
         match self {
-            CrOp::CMv | CrOp::CAdd | CrOp::CJr | CrOp::CJalr => COpcodeSpace::C2,
+            CrOp::CMv | CrOp::CAdd | CrOp::CJr | CrOp::CJalr | CrOp::CEbreak => COpcodeSpace::C2,
         }
     }
 }
@@ -1974,3 +1977,38 @@ impl CjOp {
         }
     }
 }
+
+impl CiOp {
+    pub fn funct3(&self) -> u32 {
+        // https://github.com/michaeljclark/riscv-meta/blob/master/opcodes
+        match self {
+            CiOp::CAddi | CiOp::CSlli => 0b000,
+            CiOp::CAddiw => 0b001,
+            CiOp::CAddi16sp => 0b011,
+        }
+    }
+
+    pub fn op(&self) -> COpcodeSpace {
+        // https://five-embeddev.com/riscv-isa-manual/latest/rvc-opcode-map.html#rvcopcodemap
+        match self {
+            CiOp::CAddi | CiOp::CAddiw | CiOp::CAddi16sp => COpcodeSpace::C1,
+            CiOp::CSlli => COpcodeSpace::C2,
+        }
+    }
+}
+
+impl CiwOp {
+    pub fn funct3(&self) -> u32 {
+        // https://github.com/michaeljclark/riscv-meta/blob/master/opcodes
+        match self {
+            CiwOp::CAddi4spn => 0b000,
+        }
+    }
+
+    pub fn op(&self) -> COpcodeSpace {
+        // https://five-embeddev.com/riscv-isa-manual/latest/rvc-opcode-map.html#rvcopcodemap
+        match self {
+            CiwOp::CAddi4spn => COpcodeSpace::C0,
+        }
+    }
+}