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RISC-V support #2800
RISC-V support #2800
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// TODO: totally non-portable way to change ABI | ||
unsafe { | ||
pub struct MyTargetMachine { | ||
pub target_machine: *const u8, | ||
} | ||
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let my_target_machine: MyTargetMachine = std::mem::transmute(llvm_target_machine); | ||
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*((my_target_machine.target_machine as *mut u8).offset(0x410) as *mut u64) = 5; | ||
std::ptr::copy_nonoverlapping( | ||
"lp64d\0".as_ptr(), | ||
(my_target_machine.target_machine as *mut u8).offset(0x418), | ||
6, | ||
); | ||
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std::mem::transmute(my_target_machine) | ||
} |
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This will need to be in llvm-sys or inkwell, right?
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Yes, but LLVM C API to change ABI doesn't seem to exist, so it should also be added.
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Thanks for the context.
Do you think we can create an issue on the LLVM project and add an extra comment in this source with a reference to the URL that new LLVM issue?
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Sorry for the late reply as I have been busy with my day job😢
I checked LLVM again, and I found that it seems by this change the correct ABI will be specified in LLVM 15, so I will try it.
llvm/llvm-project@4e115b7
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I have compiled and tested that on a StarFive board running Fedora, and I have some test that are failling. Do you have tests failling also on your side?
@ptitSeb Sorry for late response
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@ptitSeb on my HiFive Unmatched board, By the way some tests that seem to use filesystem were ignored. |
Yes, the traps one are also failing on my side. But I get a segfault on simd tests. The CPU doesn't have any SIMD extension, but I was assuming llvm should use non-simd path? Likewise, I haven't analysed yet. |
Also, wasmer source have evolved lately, with some new mecanism around trap and stack handling. You should try to update your fork. |
@ptitSeb I think corosensei it is compatible with RISC-V? |
There is a |
[Question]: I recently came across this and was just curious. Does this PR mean there will be Wasmer support for the likes of ESP32 MCUs? Thanks for any info. |
Mmm, there is no link between RV64 support and ESP32 support. Also ESP32 is a ressource limited platform, so an interpreter approach might be more suited. |
Description
Add RISC-V support in compiler LLVM and universal & dylib engine.
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