[Performance][Kernel] Fused_moe Performance Improvement

[charlifu]

This PR tries to improve the performance of vllm fuse moe layer by:

• Increase the thread number of moe_align_block_size_kernel to warp size.
• Replace torch.sum with customized moe_sum.
• Move moe_align_block_size_kernels.cu to moe/moe_align_sum_kernels.cu.

Motivations:

• moe_align_block_size_kernel only uses num_experts as the thread number, which causes low parallelism when handling big input size, i.e., prefilling.
• At the end of fused_moe, torch.sum is used to sum the partial results from all selected experts. But torch.sum is not optimized for this use case.

Performance Improvement (Mixtral 8x22b):
moe_sum: x6 for 8k prefill.

moe_align_block_size: x5 for 8k prefill

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[comaniac]

Thanks for the improvements! Do you have some end-to-end benchmark results to share with?

[charlifu]

Thanks for the improvements! Do you have some end-to-end benchmark results to share with?

Here are the latency (s) numbers tested on upstream (prefill, tp 2, Mixtral 8x22b, bf16):

num-prompt	input-len	w/o	w/
8	8192	14.80	14.27
16	8192	29.84	29.21
32	8192	59.55	57.36

But upstream's triton moe kernel is not tuned for rocm, so its huge overhead offsets the performance gain. On the rocm fork of vllm, we are able to see around 10% boost on tp8 for Mixtral 8x22b.

[comaniac]

Thanks for the numbers. In this case it would be great to come up with tuned configurations (we have them for some NVIDIA GPUs under https://github.com/vllm-project/vllm/tree/main/vllm/model_executor/layers/fused_moe/configs).

Also how does this PR change the performance on NVIDIA GPUs?

[charlifu]

Thanks for the numbers. In this case it would be great to come up with tuned configurations (we have them for some NVIDIA GPUs under https://github.com/vllm-project/vllm/tree/main/vllm/model_executor/layers/fused_moe/configs).

Also how does this PR change the performance on NVIDIA GPUs?

Will add the tuned configs!

Nvidia GPUs should also benefit from this PR.

[charlifu]

@comaniac
H100 e2e numbers: Mixtral 8x22b, tp8, prefill, 8k input len, 6.25% gain

num-prompt	input-len	w/o	w/
8	8192	2.00	1.88
16	8192	3.99	3.75
32	8192	8.00	7.50
64	8192	16.01	15.04
128	8192	32.01	30.07

MI300X e2e numbers: Mixtral 8x7B (tuned), tp8, prefill, 8k input len, 18% gain

num-prompt	input-len	w/o	w/
8	8192	1.26	1.01
16	8192	2.53	2.04
32	8192	5.08	4.10
64	8192	10.19	8.29
128	8192	20.53	16.78

[comaniac]

Awesome! Do you want to add AMD tuned configs in this PR or you prefer to have a follow-up PR for it?

[comaniac]

LGTM. I feel we could merge this PR first as it doesn't actually touch the MoE triton kernel.
cc @tlrmchlsmth

[tlrmchlsmth]

Nice! looks good to merge

[charlifu]

Looks like it is causing some CI failures on Nvidia side. Looking at it.

[charlifu]

The kernel test failure is fixed. I think this PR is ready to be merged. For other two failures, I noticed recently merged PRs failed on those two as well. So I suppose it is not the issue caused by this PR. @tlrmchlsmth @comaniac

[comaniac]

Ok I'll ping folks to force merge.