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[Build] Marlin: drop SM12x-specific cubins and rely on compute_80 PTX - #65540
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PR vllm-project#40923 added native SM12x cubins for the fp16/bf16 Marlin and Marlin-MoE kernels, attributing incorrect MoE output on SM12x to the 8.0+PTX fallback. That does not reproduce on current main: with Marlin built as 8.0+PTX only, the driver JIT-compiles the compute_80 PTX on SM121 and the Marlin kernel tests and an end-to-end Marlin-MoE GSM8K run match the native-cubin build. Go back to 8.0+PTX for MARLIN_ARCHS, MARLIN_BF16_ARCHS and MARLIN_MOE_ARCHS. The FP8-activation kernels keep their 8.9/12.x targets since they need e4m3 MMA, which compute_80 PTX cannot express. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: mgoin <mgoin64@gmail.com>
mgoin
requested review from
Harry-Chen,
LucasWilkinson and
tlrmchlsmth
as code owners
November 4, 2026 01:56
Removed comments regarding atomic_add for moe marlin.
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✅ Triggered Buildkite CI #99787 for commit ℹ️ This PR is 1 commit behind upstream |
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robertgshaw2-redhat
approved these changes
Nov 4, 2026
Signed-off-by: Misha Goin <mgoin64@gmail.com>
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Overview
Part of #65560.
Revert the SM12x-specific cubins that #40923 added for the fp16/bf16 Marlin and Marlin-MoE kernels, and go back to building them as
8.0+PTXonly. On SM12x the driver JIT-compiles the existing PTX (compute_80 for fp16, compute_90 for bf16), which on current main is correct and runs at the same speed.Claims
TORCH_CUDA_ARCH_LIST="8.0;9.0;12.0":_C_stable_libtorch74.6 → 70.0 MB,_moe_C_stable_libtorch35.0 → 29.0 MB, −10.6 MB total; compile time for these two targets 656 s → 593 s).~/.nv/ComputeCache); nothing once the cache is warm.Validation
All on DGX Spark (GB10, SM121), CUDA 13.0, built with
TORCH_CUDA_ARCH_LIST=12.1. Confirmed withcuobjdumpthat the PR build has no sm_120 SASS for the fp16/bf16 Marlin kernels (only sm_80/sm_90 SASS + compute_80/compute_90 PTX), so every test below goes through the JIT.tests/kernels/quantization/test_marlin_gemm.pytests/kernels/moe/test_moe.py -k marlin--moe-backend marlin, GSM8K (100 q)/health, cold JIT cache, Qwen2.5-3B-GPTQ-Int4/health, cold JIT cache, gpt-oss-20b Marlin MoEThe main column uses the precompiled main wheel. Its 2 dense failures were not investigated, and they did not occur with the PR build. The GSM8K gap is within noise for 100 questions. Output is coherent, not the gibberish described in #40923.
Details
MARLIN_ARCHS,MARLIN_BF16_ARCHSandMARLIN_MOE_ARCHSgo back to8.0+PTX(bf16 keeps9.0+PTXfor the atomicAdd path). The CUDA < 13.012.0a;12.1abranches go too.MARLIN_FP8_ARCHS/MARLIN_MOE_FP8_ARCHS) keep their 8.9/12.x targets: they use e4m3 MMA, which compute_80 PTX cannot express. [Kernel] Marlin: remove 8-bit (INT8/FP8) activation support, rely on Humming #65542 removes Marlin's 8-bit activation paths entirely in favor of Humming; the two PRs are independent._C_stable_libtorch/_moe_C_stable_libtorch). The release wheel targets many archs and already ships the sm_80 + PTX copy, so it only loses the sm_120 copy.Not a duplicate: no open PR changes these arch lists (searched "marlin PTX sm120", "marlin 12.0f").
Pull Request Checklist
I used vLLM's
/pr-checklistskill. (Mandatory for agents, optional for humans).AI assistance was used during the creation of this PR.
Design Fit: Minimizes impact on core components, reuses existing functionality, and justifies added complexity.
Testing and Validation: Validates the change and ensures any added tests are meaningful and reliable, with CI coverage or documented CI resource constraints and validation performed outside CI.
Code Quality and Style: Keeps code and comments clear and concise, and updates relevant documentation and examples.
Pull Request Contents: Includes a brief summary and relevant links, supports claims with evidence, explains root causes and implementation trade-offs, and follows the contributing guide.
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