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[ROCm] MiniMax-M3: allow the AMD monokernel decode on MiniMax-M3.1 - #65196
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… ROCm Squash of the MiniMax-M3.1 serving branch, rebased on 5d35ce3. NVIDIA: - Route NVFP4 routed experts in MXFP8 checkpoints to the CT NVFP4 MoE - NVFP4 KV cache on the MSA sparse attention path, served only by the CUTLASS Q8KV4 kernels (E4M3 query) on SM100/SM103/SM107 - NVFP4 index-K cache via the MSA Q8KV4/Q8KV8 indexers; opt-in decode context parallelism for the NVFP4 indexer at TP4 - Vendor fmha_sm100 from vllm-project/MSA dev 25c1447 - NVFP4 MSA decode past 512 sequences: Q8KV4 limits, bounded indexer and plan memory - Decode metadata before the forward: 13 ops -> 2; in-place indexer I/O, no counter reset, PDL chain for the NVFP4 sparse decode - DeepGEMM NVFP4 MegaMoE on the unified DeepGemmMegaMoEExperts layer; per-token FC1 input scales outside MegaMoE; split staging rows over programs - Fuse small-batch MoE finalize into the all-reduce + Gemma norm + MXFP8 quant - QKV+indexer MXFP8 GEMM with fused epilogue; SM100 fused dense GEMM1 - Fused QK-norm/RoPE/KV insert: persistent row-group kernel - Read aux hidden states after the deferred TP all-reduce - FA4: pass no FP8 descale for a unit per-tensor scale - Keep KV cache zeroing for mixed-precision UniformTypeKVCacheSpecs groups - Clear per-token A4 metadata for NVFP4 W4A16 MoE kernels (Marlin only) - Hand the Q8KV4 prefill a per-device split workspace - Align image preprocessing: long-side resize with detail tiers, fp32 patch embedding - NIXL KV-head re-sharding for per-head-contiguous NVFP4 pages; BLHNC layout for NIXL transfer - SimpleCPUOffload: 1 GiB HugeTLB host buffer + PreferCE batch copies Spec decode: - DSpark for MiniMax-M3.1: draft model, fixes and perf; default the draft to the checkpoint's dspark/ subfolder - Fuse the draft's q/k norm + RoPE and its context-K/V write - FLASHINFER_TS: prims_ts paged decode for non-causal draft blocks - Store the draft tokens' K/V under torch.compile - Markov sampling: one step helper, bias in the Gumbel kernel - DFlash: pad the prepared inputs in wide blocks on every platform ROCm: - Re-quantize the NVFP4 routed experts to MXFP8 (or MXFP4) at load; NVFP4 -> MXFP4 re-quantization and fused shared experts through the online quantization API - Mono decode (one FlyDSL launch per layer): native MXFP8 shared expert, top-16 sort/merge, aux hidden states, indexer CP - NVFP4 KV + NVFP4 indexer on gfx950, decode indexer CP - Tune small-M MXFP8 linears - Sequence-parallel prefill under pure TP (opt-in), with MXFP4 MoE support; TBO/DBO under pure TP; warm the microbatch threads' hipBLASLt handles at init - gfx942: avoid the load-time FP8 MoE quant crash; fall back from the fused QK-norm - Keep the NVFP4 KV-insert helpers CUDA-only so the fused kernel builds on HIP Co-authored-by: Taoyu Zhu <zhutaoyu97@gmail.com> Co-authored-by: Hongxia Yang <hongxia.yang@amd.com> Co-authored-by: qizixi <22851944+zixi-qi@users.noreply.github.com> Co-authored-by: indivats <Indira.Vats@amd.com> Co-authored-by: andyluo7 <43718156+andyluo7@users.noreply.github.com> Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg> Co-authored-by: Jee Jee Li <pandaleefree@gmail.com> Co-authored-by: fxmarty-amd <felmarty@amd.com> Co-authored-by: Jiejing Zhang <280536569+jiejingzhangamd@users.noreply.github.com> Co-authored-by: Prasun Gera <pgera@users.noreply.github.com> Co-authored-by: Dao Le <daole@inferact.ai> Co-authored-by: Isotr0py <mozf@inferact.ai> Co-authored-by: Neha Prakriya <neha.prakriya@amd.com> Co-authored-by: Summer Yang <girasoley@inferact.ai> Co-authored-by: Zhewen Li <jerven.vllm@gmail.com> Co-authored-by: Zijing Liu <liuzijing2014@users.noreply.github.com> Co-authored-by: xiaozhoupy <peiyuanzhou1994@gmail.com> Co-authored-by: v <v@inferact.ai> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
…wn PRs (vllm-project#63490) Signed-off-by: Taoyu Zhu <zhutaoyu97@gmail.com> Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
…ssage (vllm-project#63492) Signed-off-by: Seungmin Kim <8457324+ehfd@users.noreply.github.com>
Accept an NVFP4 KV and indexer cache (the fused launch starts after attention), sparse attention on the leading dense-FFN layers, and serve the fused launch a lossless BF16 copy of MXFP8 qkv/o projections. Signed-off-by: Limpus, David <dlimpus@amd.com>
The mxfp4 variant can now pick the post-attention monokernel, which keeps the NVFP4 KV and indexer caches but refuses DSpark. Mono stays the default. Signed-off-by: Limpus, David <dlimpus@amd.com>
minimax-m31-flash was deleted after vllm-project#64111 merged into main, so retarget this branch at main. The old base (a0ea941) is not in main's history, so take main's tree and re-apply this PR's four-file diff on top; it applied cleanly. Signed-off-by: Limpus, David <dlimpus@amd.com>
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Replaces #64273, which GitHub closed when its base branch
minimax-m31-flashwas deleted after #64111 merged into main.Purpose
Let the AMD fused-FFN decode launch (
--monokernel, Model Runner V2) run on MiniMax-M3.1. Today it refuses the checkpoint for three reasons:spec.pynow acceptsnvfp4for the KV and indexer caches as well as FP8.weights.pygives it a dequantized copy. E4M3 times a power-of-two scale is exact in BF16, so the copy is lossless. The stock path keeps serving the MXFP8 weights.Serving M3.1 this way also needs
VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS=1,--quantization-config.targets '{"*shared_experts*": "mxfp4"}'andindexer_decode_cp=false. The shared-expert requant is lossy, and the accuracy gate is still pending (see below).The recipe gets a
monokernelmode undermono_decodefor the mxfp4 variant, carrying those settings.monostays the default. The monokernel path accepts only EAGLE3 speculation, so it can't run with the recipe's DSpark draft; the mode description says to turn Speculative decoding off. The recipe schema has no way to express that conflict.Test Plan
tests/models/minimax_m3/amd_specialized_decode/test_runtime.py. The refusal test now puts a dense layer inside the fused range, and a new test accepts the M3.1 layout.node scripts/validate-source.mjs --source vllm --dir recipesfrom a vllm-project/recipes checkout.Test Result
MiniMax-M3 FFN launch: rows (1..16), 57 sparse layers per step. Batches above 16 rows use the stock path.KV capacity is 16.58M tokens, against 16.91M for the baseline. The C64 gain can't come from the fused launch, which stops at 16 rows; it's most likely the MXFP4 shared experts.
DSpark caveat. The baseline in this table isn't the recipe's real default. On AMD the recipe turns DSpark on (3 speculative tokens), and this path refuses DSpark, so its fair comparison is against the same baseline with DSpark. That run is pending. Until it lands, these numbers show the gain only for deployments that run without speculative decoding, and they may not beat the recipe default at all.
Accuracy: pending.