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[ROCm] MXFP8 linear: one tile row for 17-64 token decode batches - #64195

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amd-dlimpus:cursor/rocm-mxfp8-decode-tiles-a294
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amd-dlimpus:cursor/rocm-mxfp8-decode-tiles-a294

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@amd-dlimpus amd-dlimpus commented Oct 28, 2026 •

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Overview

On ROCm (gfx950), RocmDotScaledMxfp8LinearKernel uses a BLOCK_M=16 tile for every decode batch up to M=64, so from 17 rows on the grid re-reads the whole weight from HBM once per 16 rows. This PR gives 17 ≤ M ≤ 64 a single tile row (BLOCK_M 32 or 64). It changes _select_cfg only.

On MiniMax-M3 at M=64 it is 1.2–2.0x per GEMM, an estimated ~1.8 ms/step saved at TP2 and ~0.8 ms at TP4 (of 39.7 ms at C64).

Validation

Correctness. tests/kernels/quantization/test_rocm_mxfp8_linear.py: 113 passed on MI355X. It adds the M3 TP4 shapes at M ∈ {16, 17, 32, 33, 48, 64, 65}, wq_b (K=1280) at M=48, and M3 TP2 qkv at M=32.

Microbenchmark. Single MI355X, 200 CUDA-graph-replayed launches over more than 512 MB of rotating weight copies, so every launch reads its weight from HBM. Without the rotation the 256 MB MALL hides the re-reads. Activation quant is excluded. Times in µs, main → this PR, M=32 / M=64:

MiniMax-M3 (N×K) M=32 M=64
TP2 qkv 4992×6144 18.2 → 13.7 26.4 → 15.7
TP2 o 6144×4096 14.7 → 10.3 22.2 → 11.6
TP2 sh gate_up 3072×6144 10.7 → 9.0 18.6 → 13.4
TP2 sh down 6144×1536 5.4 → 5.3 9.1 → 5.8
TP4 qkv 2560×6144 10.2 → 8.9 17.6 → 13.4
TP4 o 6144×2048 9.0 → 6.3 14.1 → 7.0
TP4 sh gate_up 1536×6144 8.0 (same) 10.1 → 8.8
TP4 sh down 6144×768 4.2 → 4.3 5.4 → 4.6

DeepSeek-V4.1 attention linears (V41_ATTN_SHAPES), same method, one run per arm:

V4.1 (N×K) M=32 M=64
TP4 wqa_wkv 1792×5120 7.1 → 7.1 9.4 → 7.8
TP4 wq_b 8192×1280 6.5 → 6.0 9.6 → 6.5
TP4 wo_a 2048×4096 6.2 → 6.5 8.7 → 9.3
TP4 wo_b 5120×2048 8.6 → 6.1 13.1 → 7.0
TP4 per layer 28.4 → 25.7 (−9%) 40.8 → 30.6 (−25%)
TP8 wqa_wkv 1792×5120 7.1 → 7.1 9.4 → 7.8
TP8 wq_b 4096×1280 5.5 → 5.7 6.3 → 6.1
TP8 wo_a 1024×4096 5.7 → 5.7 6.2 → 6.3
TP8 wo_b 5120×1024 5.1 → 4.3 6.8 → 4.5
TP8 per layer 23.4 → 22.8 (−3%) 28.7 → 24.7 (−14%)

Known regressions.

  • V4.1 TP4 wo_a at M=64 regresses from 8.7 to 9.3 µs; the 64-row tile is picked because N ≥ 2048. A 32-row tile would fix it but slows M3 TP4 qkv and TP2 gate_up (K=6144) from about 13.4 to 17 µs, so it is left as is.
  • TP4 wo_a and TP8 wq_b at M=32 (+0.2–0.3 µs) and M3 TP4 sh down at M=32 (4.2 → 4.3) are within noise.

Pending: end-to-end decode A/B on main (MiniMax-M3, TP4), waiting on 4 GPUs.

Details

  • Up to M=16 the narrow 16×16 grid is right, because it maximizes the CTAs streaming the weight. Each extra 16-row tile row streams the weight again, which is 4x the bytes at M=64.
  • With N < 2048, BLOCK_M=64 leaves too few N-tiles, so those shapes use 32 and keep the old tile at M ≤ 32. Otherwise TP4 sh gate_up regresses from 10.1 to 13.1 µs.
  • M ≤ 16 and M > 64 are unchanged. M=128 also misses the sweep's best tile and is left for a follow-up.

Pull Request Checklist
  • I used vLLM's /pr-checklist skill. (Mandatory for agents, optional for humans).

  • AI assistance was used during the creation of this PR.

  • Design Fit: Minimizes impact on core components, reuses existing functionality, and justifies added complexity.

  • Testing and Validation: Validates the change and ensures any added tests are meaningful and reliable, with CI coverage or documented CI resource constraints and validation performed outside CI.

  • Code Quality and Style: Keeps code and comments clear and concise, and updates relevant documentation and examples.

  • Pull Request Contents: Includes a brief summary and relevant links, supports claims with evidence, explains root causes and implementation trade-offs, and follows the contributing guide.

A BLOCK_M=16 tile re-streams the whole weight once per 16 rows. For
16 < M <= 64, cover M with a single tile row (BLOCK_M 32 or 64). Timed
with weights read from HBM (rotating copies larger than the MALL), this
is 1.2-1.9x faster on MiniMax-M3 TP2/TP4 dense shapes at M=32/64.
M <= 16 is unchanged. Adds M3 TP4 shapes to the correctness test.

Signed-off-by: Limpus, David <dlimpus@amd.com>
Signed-off-by: Limpus, David <dlimpus@amd.com>
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@mergify mergify Bot added the rocm Related to AMD ROCm label Oct 28, 2026
@github-project-automation github-project-automation Bot moved this to Todo in AMD Oct 28, 2026
…ecode-tiles-a294

Signed-off-by: Limpus, David <dlimpus@amd.com>
Covers wq_b's K=1280 at M=48 (BLOCK_K=256) and the largest new tile,
32x32x1024 with 2 stages, used by the TP=2 qkv (N=4992) at M=32.

Signed-off-by: Limpus, David <dlimpus@amd.com>
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mergify Bot commented Oct 29, 2026

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This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @amd-dlimpus.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

@mergify mergify Bot added the needs-rebase label Oct 29, 2026
jiacao-amd added a commit to jiacao-amd/vllm that referenced this pull request Nov 2, 2026
Select gfx950 tiles by M, local N and K while preserving the existing
fallback outside the tuned range. Fold the M48 QKV exception into the
table and use the narrow tile from vllm-project#64195 for V4.1 wqa/wkv M48 and M64.

Extend the existing linear tests across the tuned buckets and TP2 shapes.

Co-authored-by: OpenAI Codex
Co-authored-by: Claude Code
Signed-off-by: jiacao-amd <jiahui.cao@amd.com>

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