[douglas-reid]

Summary

In GateLinear.forward, Tier 1 (ll_bf16_gemm, the CuTe DSL low-latency BF16->FP32 router GEMM for M <= 16 on SM90+) was gated by an inline Python conditional on x.shape[0]:

if (
    self.allow_ll_bf16_gemm
    and x.shape[0] <= self.LL_BF16_MAX_TOKENS
    and x.dtype == torch.bfloat16
):
    output = ll_bf16_gemm(x, self.weight)

Unlike Tier 2 (torch.ops.vllm.fp32_router_gemm_dispatch) and Tier 4 (torch.ops.vllm.rocm_bf16x3_router_gemm_dispatch), Tier 1 did not wrap its runtime x.shape[0] check in a custom op:

• When GateLinear is called from a @support_torch_compile model forward(), vLLM's TorchCompileWithNoGuardsWrapper drops all Dynamo guards (skip_all_guards_unsafe / guard_filter_fn).
• Consequently, the Python branch x.shape[0] <= 16 is evaluated once during the initial torch.compile trace (e.g. M = 2048 during warmup) and frozen to False for all subsequent decode batch sizes (M = 1..16), permanently bypassing ll_bf16_gemm in favor of the Tier 5 torch.mm(x, weight.T, out_dtype=torch.float32) fallback.
• The Python branch is wrong regardless of which size traces first (an M <= 16 first trace would freeze ll_bf16_gemm in at M = 8192), which is why Tiers 2 and 4 already use custom ops.

Scope & Trade-offs

• Affected models: Tier 1 requires bf16 weights + out_dtype=torch.float32 + bias=False + unquantized + SM90+ and a gate called from @support_torch_compile model code. On main, that is Gemma 4 (Gemma4Router.proj), Nemotron-H (force_fp32_compute=True keeps bf16 weights when specialized kernels exist), and MiMo-V2 when moe_router_dtype is bfloat16. Most models migrated in [MoE] Use GateLinear for all MoE models #58234 lack out_dtype=torch.float32, use fp32 gate weights, set bias=True (gpt-oss), or pass gate= into the opaque moe_forward_shared custom op (DeepSeek family) and are unaffected.
• Batch invariance: After this PR, Gemma 4 decode (M <= 16) and prefill (M > 16) use different GEMM kernels, so router logits may differ in the last ULP across batch sizes; this is Tier 1's pre-existing design (DeepSeek already behaves this way) and VLLM_BATCH_INVARIANT gating is handled at init by [Bugfix] Keep GateLinear batch invariant under VLLM_BATCH_INVARIANT #59985.
• Warmup: The c1_pdl (M = 1) warmup gap is addressed by [7/N][warmup][DSv4] Migrate router GEMM kernels #50177.

---

Changes

1. vllm/model_executor/layers/fused_moe/router/gate_linear.py:
   • Register custom op torch.ops.vllm.ll_bf16_router_gemm_dispatch(x, weight, max_tokens) (mirroring fp32_router_gemm_dispatch and rocm_bf16x3_router_gemm_dispatch) so 0 < x.shape[0] <= max_tokens is evaluated dynamically at runtime outside the compiled FX graph, calling ll_bf16_gemm(x.contiguous(), weight) for 0 < m <= max_tokens and falling back to Tier 5 torch.mm(x, weight.T, out_dtype=torch.float32) otherwise.
2. tests/kernels/test_ll_bf16_gemm.py:
   • Update test_gate_linear_torch_compile_dynamic_m_dispatch to drop guards via guard_filter_fn and execute decode calls (M in (1, 4, 16)) under torch.compiler.set_stance("fail_on_recompile") after tracing at M = 32, emulating TorchCompileWithNoGuardsWrapper so the test fails on main (AssertionError: assert [] == [1, 4, 16]) and passes with the custom op.

---

Benchmarks (NVIDIA H100 80GB HBM3)

1. Gemma4DecoderLayer Subgraph (VllmCompile + CUDAGraph, 30 Layers)

Full Gemma4DecoderLayer FFN + MoE + Router + 7 RMSNorms subgraph (google/gemma-4-26B-A4B-it, K=2816, E=128, top_k=8) compiled with CompilationMode.VLLM_COMPILE and captured in a CUDAGraph:

Tokens (T)	main (us / layer)	This PR (us / layer)	Delta / Layer	30-Layer Subgraph Delta	Speedup
1	81.03 us	77.18 us	-3.85 us	-115.5 us / step	+4.99%
2	119.34 us	115.61 us	-3.73 us	-111.9 us / step	+3.23%
4	169.49 us	166.29 us	-3.20 us	-96.0 us / step	+1.92%
8	278.41 us	275.34 us	-3.07 us	-92.1 us / step	+1.11%

2. End-to-End google/gemma-4-26B-A4B-it Latency (input_len=128, output_len=64)

Measured on H100 80GB HBM3 (dtype=bfloat16, VLLM_COMPILE + full/piecewise CUDAGraphs, median of 10 iterations after 3 warmup iterations). Batch size 32 (M = 32 > LL_BF16_MAX_TOKENS = 16) uses Tier 5 torch.mm in both main and this PR and is unchanged as expected:

Batch Size	main Latency (ms)	This PR Latency (ms)	Delta (ms)	Speedup	Notes
1	295.31 ms	288.06 ms	-7.25 ms	+2.52%	-115.1 us / decode step (-3.84 us / layer across 30 layers)
8	350.02 ms	345.49 ms	-4.53 ms	+1.31%	Uses ll_bf16_gemm split-K kernel (5 <= M <= 16)
16	385.49 ms	380.82 ms	-4.67 ms	+1.23%	Uses ll_bf16_gemm split-K kernel (5 <= M <= 16)
32	480.68 ms	480.30 ms	-0.38 ms	+0.08%	Unchanged as expected (M = 32 > 16 falls back to Tier 5 torch.mm)

3. Isolated GateLinear Router GEMM Under Guard-Free torch.compile + CUDAGraph

In main, TorchCompileWithNoGuardsWrapper drops all Dynamo guards (options={"guard_filter_fn": lambda x: [False for _ in x]}) and traces first at M = 2048, freezing Tier 5 torch.mm(x, weight.T, out_dtype=torch.float32) into the compiled graph (plain torch.compile(dynamic=True) without guard_filter_fn retains guards and recompiles, so guard_filter_fn is required to reproduce the frozen production graph):

Model Shape (K -> E)	M	main (Frozen Tier 5 torch.mm)	This PR (ll_bf16_router_gemm_dispatch)	Speedup	Latency Reduction
Gemma 4 26B-A4B (2816 -> 128)	1	6.54 us	2.59 us	2.52x	-60.4%
Gemma 4 26B-A4B (2816 -> 128)	2	6.48 us	3.23 us	2.01x	-50.2%
Gemma 4 26B-A4B (2816 -> 128)	4	6.49 us	3.45 us	1.88x	-46.8%
Gemma 4 26B-A4B (2816 -> 128)	8	6.46 us	5.31 us	1.22x	-17.8%
Gemma 4 26B-A4B (2816 -> 128)	16	6.75 us	5.89 us	1.15x	-12.7%

Reproducible Microbenchmark Harness

import torch
from vllm.model_executor.kernels.linear.cute_dsl.ll_bf16 import (
    ll_bf16_gemm,
    ll_bf16_gemm_c1_pdl_kernel,
    ll_bf16_gemm_kernel,
)
from vllm.model_executor.layers.fused_moe.router.gate_linear import GateLinear

device = "cuda"
K, E = 2816, 128
ll_bf16_gemm_c1_pdl_kernel.warmup(shapes=[(K, E)], m_values=(1,))
ll_bf16_gemm_kernel.warmup(shapes=[(K, E)], m_values=range(2, 17))

weight = torch.randn(E, K, device=device, dtype=torch.bfloat16) * 0.02


class MainGate(torch.nn.Module):
    def __init__(self, w):
        super().__init__()
        self.weight = torch.nn.Parameter(w, requires_grad=False)

    def forward(self, x):
        if x.shape[0] <= 16:
            return ll_bf16_gemm(x, self.weight)
        return torch.mm(x, self.weight.T, out_dtype=torch.float32)


class PRGate(torch.nn.Module):
    def __init__(self, w):
        super().__init__()
        self.weight = torch.nn.Parameter(w, requires_grad=False)

    def forward(self, x):
        return torch.ops.vllm.ll_bf16_router_gemm_dispatch(
            x, self.weight, GateLinear.LL_BF16_MAX_TOKENS
        )


# Emulate vLLM's TorchCompileWithNoGuardsWrapper by dropping all Dynamo guards
# and tracing first at M=2048.
compile_opts = {"guard_filter_fn": lambda entries: [False for _ in entries]}
main_compiled = torch.compile(
    MainGate(weight), fullgraph=True, dynamic=True, options=compile_opts
)
pr_compiled = torch.compile(
    PRGate(weight), fullgraph=True, dynamic=True, options=compile_opts
)

x_warmup = torch.randn(2048, K, device=device, dtype=torch.bfloat16)
main_compiled(x_warmup)
pr_compiled(x_warmup)


def bench_cudagraph(fn, x, repeats=50, trials=31):
    for _ in range(10):
        fn(x)
    torch.cuda.synchronize()
    g = torch.cuda.CUDAGraph()
    with torch.cuda.graph(g):
        for _ in range(repeats):
            fn(x)
    for _ in range(10):
        g.replay()
    torch.cuda.synchronize()
    times = []
    for _ in range(trials):
        s = torch.cuda.Event(enable_timing=True)
        e = torch.cuda.Event(enable_timing=True)
        s.record()
        g.replay()
        e.record()
        torch.cuda.synchronize()
        times.append(s.elapsed_time(e) * 1000.0 / repeats)
    times.sort()
    return times[len(times) // 2]


for m in (1, 2, 4, 8, 16):
    x = torch.randn(m, K, device=device, dtype=torch.bfloat16)
    t_main = bench_cudagraph(main_compiled, x)
    t_pr = bench_cudagraph(pr_compiled, x)
    print(f"M={m:2d}: main={t_main:.2f} us | PR={t_pr:.2f} us | speedup={t_main/t_pr:.2f}x")

---

Test Plan

• pytest tests/kernels/test_ll_bf16_gemm.py -v (138 passed on NVIDIA H100 80GB HBM3, plus verified test_gate_linear_torch_compile_dynamic_m_dispatch fails when GateLinear.forward is reverted to main)

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[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @douglas-reid.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @douglas-reid.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork