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--disable-custom-all-reduce only removed the custom all-reduce kernel from the TP group. On Hopper and Blackwell the FlashInfer and symmetric-memory all-reduce stayed on, and at -O2 so did the FlashInfer all-reduce + RMSNorm fusion, so all-reduce did not fall back to NCCL as documented. Gate them on the flag too, as QuickReduce and AITER all-reduce already are on ROCm, and turn the fusion off by default when the flag is set. Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Roy Zheng <39311511+roy6n23@users.noreply.github.com>
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Documentation preview: https://vllm--60011.org.readthedocs.build/en/60011/ |
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A user-side data point: in #60660 (a FlashInfer MNNVL all-reduce crash on 4x H20 with vLLM 0.30.0) the reporter kept AI assistance: Claude Code found the issue and drafted this comment; I checked it against the issue. |
Overview
Fixes #59987.
--disable-custom-all-reduceis documented as "Disable the custom all-reduce kernel and fall back to NCCL", but on Hopper and Blackwell it only removes theCUSTOMbackend. The TP group keeps the FlashInfer and symmetric-memory all-reduce, and at the default-O2the FlashInfer all-reduce + RMSNorm fusion stays on. This PR makes the flag turn those off too, so all-reduce falls back to NCCL.Claims
--disable-custom-all-reduce, the TP group's all-reduce backends are['PYNCCL']and the all-reduce + RMSNorm fusion is off (an explicitpass_config.fuse_allreduce_rms=Truestill turns it on).Validation
2x H100 SXM (NV18),
vllm/vllm-openai:nightly-18f8f96025b556071eb627076f94df560fbd3a22with this PR's diff applied to the installed package (18f8f9602is 15 commits behind this PR's base and none of them touch the changed files),Qwen/Qwen2.5-1.5B-Instruct, TP=2, default-O2:allreduce_rmsfusion--disable-custom-all-reduce['FLASHINFER', 'PYNCCL']allreduce_fusion_kernel_oneshot_lamport, 0 NCCL all-reduce--disable-custom-all-reduce['PYNCCL']ncclDevKernel_AllReduce_Sum_bf16_RING_LL['FLASHINFER', 'CUSTOM', 'PYNCCL']allreduce_fusion_kernel_oneshot_lamport-cc.pass_config.fuse_allreduce_rms=True['PYNCCL']allreduce_fusion_kernel_oneshot_lamport1824 is 57 all-reduces per forward pass (the embedding plus two per layer, 28 layers) times 32 forward passes, so on main with the flag every all-reduce in the model ran in FlashInfer and none in NCCL. The greedy completion of the profiled request was the same in all four runs.
SYMM_MEMis missing from these lists because multicast does not work on this host:SymmMemCommunicatorlogs "symmetric memory multicast operations are not supported" after the CUDA driver returns error 401, the same error that made NCCL's NVLS setup fail inncclCommInitRank, so all four runs usedNCCL_NVLS_ENABLE=0. On the host in #59987 (2x H100, vLLM 0.30.0) the default list was['FLASHINFER', 'CUSTOM', 'SYMM_MEM', 'PYNCCL']and the flag left['FLASHINFER', 'SYMM_MEM', 'PYNCCL']. The unit test below covers the symmetric-memory gate.Reproduction commands
All four runs were on the same pod. The first row used the image as is; for the other three the
vllm/part of this PR's diff was applied to the installed package withpatch -p1.Counting the all-reduce kernels in each rank's trace:
It also prints 32
ncclDevKernel_AllGather_RING_LLlaunches in every run: the logits processor's all-gather across vocab shards, one per forward pass, not all-reduces.Tests:
test_disable_custom_all_reduce_falls_back_to_nccl(tests/distributed/test_comm_ops.py, runs on CPU with stand-in backends): builds a TPCudaCommunicatorwith custom all-reduce disabled and checks that an all-reduce goes to pynccl, not to FlashInfer, FlashInfer PCIe IPC or symmetric memory. It fails on main and passes with the fix.test_allreduce_rms_fusion_default_follows_disable_custom_all_reduce(tests/test_config.py): on a platform patched to look like SM90 with FlashInfer, the fusion default is on without the flag and off with it. The flag case fails on main.test_flashinfer_all_reduce_precedes_nccland the threetest_multi_process_tensor_parallel[*-2]cases, 7 passed.tests/distributed/test_comm_ops.pyandtests/test_config.py: 435 passed, 17 skipped, 19 failed. The same 19 fail on main in that container (gated HF repos and CPU-platform defaults).pre-commit run --files <changed files>: all hooks pass.Duplicate check: no open PR references #59987. Open PRs that match
disable_custom_all_reduceorVLLM_ALLREDUCE_USE_FLASHINFERtouch other things (#55835 cross-node MNNVL groups, #59730 IPC all-gather, #47751 custom all-reduce on sm_12x).Details
The flag only reaches
_ENABLE_CUSTOM_ALL_REDUCE, which gatesCustomAllreduce, and on ROCm also AITER and QuickReduce all-reduce. FlashInfer all-reduce (on by default since #52998) and symmetric-memory all-reduce were added later with their own env vars and never tied to the flag. The fusion default,enable_allreduce_rms_fusion, doesn't look at it either. So on SM 9.0 / 10.x the flag leaves most all-reduces on FlashInfer: at-O2the ones followed by RMSNorm run inside the fused kernel, and the rest go through['FLASHINFER', 'SYMM_MEM', 'PYNCCL'].The change:
CudaCommunicator: FlashInfer, FlashInfer PCIe IPC and symmetric-memory all-reduce also require_ENABLE_CUSTOM_ALL_REDUCE, the way AITER and QuickReduce already do.enable_allreduce_rms_fusionreturns False when the flag is set. This only changes the default; an explicitfuse_allreduce_rmsstill wins.--helptext) anddocs/design/fusions.mdnow say what it turns off.Things to be aware of:
VLLM_ALLREDUCE_USE_*ones) would be the natural counterpart._can_use_flashinferinfused_allreduce_gemma_rms_norm.py(DeepSeek V3.2, Kimi K3, MiniMax M3). I left those out to keep this PR small and can gate them in a follow-up if you want.test_tp2_ar_rms.py, set it toFalse.VLLM_ALLREDUCE_USE_FLASHINFER=0 VLLM_ALLREDUCE_USE_SYMM_MEM=0gives NCCL only. At-O2the fusion also has to be off (-cc.pass_config.fuse_allreduce_rms=False).AI assistance: Claude Code (Claude Opus 5.5) drafted the patch and the tests and ran the validation above in a local CPU container and on a rented 2x H100 pod. I reviewed every changed line and the results.
Pull Request Checklist
I used vLLM's
/pr-checklistskill. (Mandatory for agents, optional for humans).AI assistance was used during the creation of this PR.
Design Fit: Minimizes impact on core components, reuses existing functionality, and justifies added complexity.
Testing and Validation: Validates the change and ensures any added tests are meaningful and reliable, with CI coverage or documented CI resource constraints and validation performed outside CI.
Code Quality and Style: Keeps code and comments clear and concise, and updates relevant documentation and examples.
Pull Request Contents: Includes a brief summary and relevant links, supports claims with evidence, explains root causes and implementation trade-offs, and follows the contributing guide.