[nehaprakriya]

Purpose

Fuses the ragged indptr prefix sum into _pack_global_topk_ragged_kernel for the DSA decode index build on AMD gfx950 (MI355X), eliminating dispatch overhead that CUDA never incurs.

compute_global_topk_ragged_indices_and_indptr runs 38× per decode step (once per sparse attention layer). On ROCm, the previous code called _build_indptr_from_lengths which launched torch.zeros + torch.cumsum (a rocprim lookback scan) to prefix-sum 193 int32s. Measured cost: ~305 µs/step of pure kernel dispatch. CUDA never pays this: build_flashinfer_mixed_sparse_indices in common/ops/cache_utils.py emits its indptr inside the pack kernel's registers in a single launch.

This change ports that approach to ROCm: each token program derives its own indptr offset via a masked tl.sum over NTOK_PAD lanes in-register and stores its own entry before the early-return. topk_indptr is now torch.empty (no pre-zeroing needed since every entry is written by the kernel). The else: topk_indptr.zero_() branch covers the degenerate empty case. _build_indptr_from_lengths is removed.

Result: 4 → 2 graph nodes per call, 152 → 76 kernel launches/step (−50%), 1.69× on the cluster, bitwise-identical output.

This is not a duplicate of any open PR. PR #56638 ("Re-enable the fused combine_topk_swa_indices on gfx950") addresses a different function on the prefill path. AI assistance was used; every changed line has been reviewed and verified.

Test Plan

# Correctness + launch count verification (bitwise match at 6 shapes,
# including 768-row max batch, ragged rows, invalid rows)
python eval/eval_e2a_fused_ragged_index_build.py

# Profile to confirm graph node count: 4.0 -> 2.0 per call
python eval/eval_kernel_attribution.py

# E2e benchmark (MI355X, TP=4, C=32, agentic-coding, 600 s):
python bench.py --scenario agentx --conc 32 --duration 600

Test Results

Component (gfx950, measured on live import path via profiler):

Metric	Before	After
Graph nodes / call	4.0	2.0
Kernel launches / decode step	152	76 (−50%)
Cluster speedup	1.00×	1.69×
Per-step saving	—	126.6 µs

Scaling: flat across 1→768-row sweep, confirming dispatch-bound mechanism. Output bitwise-identical at all 6 measured shapes.

End-to-end (MI355X, TP=4, C=32, agentic-coding, 600 s — this change in isolation):

Metric	Before	After	Δ
Output throughput	325.28 tok/s/chip	324.91 tok/s/chip	−0.1% (within noise)
p90 interactivity	64.76 tok/s/user	65.97 tok/s/user	+1.9%
p90 TPOT	15.4 ms	15.2 ms	−1.8%

Note: the throughput delta is within the measured noise band. The primary value of this change is the 50% launch reduction, which reduces CUDA-graph replay overhead and creates headroom for future kernel additions within the decode step budget.

• The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)".
• The test plan, such as providing test command.
• The test results, such as pasting the results comparison before and after, or e2e results
• (Optional) The necessary documentation update, such as updating supported_models.md and examples for a new model.

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[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @nehaprakriya.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork