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Documentation preview: https://vllm--57325.org.readthedocs.build/en/57325/ |
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Reuse GPU hits in place and load CPU hits by position through a memoized joint lookup, preserving attention-specific matching, allocation limits, copy-on-write, and transfer ownership. Attribute cache statistics and events to their actual GPU/CPU sources. Keep MultiConnector and private-pool groups on the existing lookup path. Cover interleaved residency, sparse matching, admission, lifecycle cleanup, and cache events in the existing test suites. Co-authored-by: Codex Co-authored-by: GPT-6 Astra Signed-off-by: Yudong An <43297577+iMMIQ@users.noreply.github.com>
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Keep the upstream replay-window and pending CPU-pin cleanup fixes. Exclude joint CPU load targets from worker-side zeroing to avoid racing asynchronous transfers, and cover zeroing in the existing residency tests. Co-authored-by: Codex Signed-off-by: Yudong An <43297577+iMMIQ@users.noreply.github.com>
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Event-side notes only; I didn't review the lookup itself.
The store emitted after a joint load doesn't match the dense shape consumers expect for full-attention groups. cache_blocks masks out the interleaved GPU hits via _joint_cache_reused_blocks, but cache_full_blocks still spans token_ids from num_cached_block to num_full_blocks, so for gcgg the event is block_hashes=[h1] with 48 tokens, and for gcgc it is [h1, h3] with blocks 1-3's tokens, so h3 lines up with block 2. This is in the default incremental mode, so every subscriber sees it: llm-d skips it as non_dense_block_span (the loaded GPU copy is never indexed), and Dynamo's create_stored_blocks walks tokens positionally and indexes h3 under block 2's tokens. Wonder if we could emit one BlockStored per contiguous run of newly cached blocks (parent = hash before the run, token_ids = the run), either by splitting in cache_full_blocks when a mask hides cached positions or by caching each CPU run separately on the joint path. That keeps each event dense and lines up with the dense-run direction in #44488 / #58121.
On full reports, one event per contiguous GPU run with parent_block_hash set is self-consistent, and it's the same per-run shape suggested on #57358, so I think we should converge the two PRs on it (both change the emit_cached_block_events signature, start_block here vs cached_blocks / num_cached_tokens there). It does change the documented contract though: #60616 says a full report starts at the first block with a nil parent, and with a CPU block 0 the joint path emits no nil-parent event at all. Whichever lands second should update docs/features/kv_events.md and tests/v1/core/test_kv_events_contract.py.
Two smaller consistency points:
- The joint path emits the
fullreport inallocate_slotsafter admission, while the non-joint path emits it inget_computed_blockson every lookup. The admission timing seems better; might be worth stating which one we intend. emit_joint_cached_block_eventsusesmanager.block_size(DCP-scaled) whileemit_cached_block_eventsstill useskv_cache_spec.block_size, so under DCP the two paths disagree until #50118 lands.
| reachable_boundaries=reachable_boundaries, | ||
| dcp_world_size=self.dcp_world_size, | ||
| ) | ||
| if reused := self._joint_cache_reused_blocks.get(request.request_id): |
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The mask keeps the reused GPU positions out of the hash map, but cache_full_blocks still sets token_ids to [num_cached_blocks, num_full_blocks), so the resulting BlockStored has fewer hashes than token blocks, e.g. [h1, h3] over blocks 1-3 for gcgc, so h3 pairs with block 2's tokens. llm-d drops it as non_dense_block_span and Dynamo indexes h3 under the wrong tokens. I think we want one event per contiguous run of newly cached blocks here, so each event's parent, hashes and tokens stay aligned.
| group_idx, | ||
| ) | ||
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| def emit_joint_cached_block_events( |
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One event per contiguous GPU run with a real parent looks right to me, and matches what was suggested on #57358 for null-padded hits. Worth noting it changes the full-mode shape from "starts at block 0 with a nil parent": a CPU block 0 gives no nil-parent event at all, and later runs name a parent whose GPU store only arrives after the load. Might be worth a line in the description and a contract-doc update once #60616 lands.
| parent_block_hash: ExternalBlockHash | None = None | ||
| start_token_idx = 0 | ||
| end_token_idx = num_cached_blocks * block_size | ||
| parent_block_hash = ( |
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nit: with start_block the docstring's "blocks reused from prefix cache" now also covers mid-prefix runs, and if a run can end on a partial (copy-on-write) block, block_hashes[i] / end_block * block_size hit the same partial-tail issue #57358 is fixing for the main path. Might be worth an assert-free guard or a test with hash_block_size < block_size.
| ) | ||
| manager.cache_blocks(request, 4 * BLOCK_SIZE) | ||
| events = manager.block_pool.take_events() | ||
| assert [event.block_hashes for event in events] == [[hashes[1]]] |
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nit: this only checks block_hashes, so the 48-token span on the post-load event isn't caught. Might be worth asserting token_ids length and parent for each event, and adding a gcgc layout plus an incremental-mode case, since that's the shape every consumer sees.
…tails Cache CPU load targets in contiguous runs so event hashes, tokens, parents, and extra keys stay aligned. Bound reused partial tails by the accepted hit and document full-report ordering and admission timing. Use block pool ownership for source classification and reduce redundant test setup and parameter combinations. Validation: 505 relevant pytest cases passed; eager/lazy scratch-group checks passed; pre-commit and Python 3.12 mypy passed. Real-model evaluations were not rerun for this update. Co-authored-by: Codex Signed-off-by: Yudong An <43297577+iMMIQ@users.noreply.github.com>
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Preserve lookahead hashes in dense reuse events, refresh eager CPU LRU entries on joint admission, and retain upstream bounds for prompt scoring and auxiliary outputs. Update joint Mamba coverage for the supported align mode and exercise reused lookahead events and joint CPU LRU refresh. Validation: 628 cache/connector tests passed; 440 scheduler, manager, worker and auxiliary-output tests passed. Three multi-GPU scheduler tests fail identically on unmodified main on this single-GPU host. Qwen3-0.6B passed three cold/warm comparisons with real interleaved CPU loads. Co-authored-by: Codex Signed-off-by: Yudong An <43297577+iMMIQ@users.noreply.github.com>
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This pull request has merge conflicts that must be resolved before it can be |
Purpose
Background
We deploy DeepSeek V4 Flash Vision Exp with vLLM Ascend v0.27 in our internal network, with Simple CPU Offload enabled. During operation, we observed a cache miss rate exceeding 10%. Investigation showed that some reusable cache entries were not being retrieved due to the unimplemented TODO in
vllm/v1/simple_kv_offload/manager.py: the existing API only matches a CPU suffix following the GPU prefix, rather than searching for a complete valid prefix across both pools.After implementing joint lookup, we ported the change to the v0.27 branch in our fork and redeployed it in the same environment. The deployment has been running for five days, with normal operation and successful retrieval of cache entries previously affected by this limitation.
This PR targets upstream main. The deployment observations above come from the v0.27 backport in our fork.
Changes
Support valid prefixes composed of interleaved GPU and CPU cache blocks, replacing the limitation of matching a GPU prefix followed by a CPU suffix.
For example, given a
GPU → CPU → GPUcache layout, reuse both GPU blocks directly and allocate and load a target block only for the middle CPU block. When both pools contain a required block, prefer the GPU copy.The implementation:
Relationship to related work
This PR implements joint lookup for interleaved GPU/CPU prefixes in
SimpleCPUOffloadConnector. The related #52773 / #52774 address boundary backfill inOffloadingConnector, so the connector and implementation scope differ.Test Plan
Cover the following behaviors:
Regression command after the latest code cleanup:
Run pre-commit on modified files, along with Python 3.10/3.12 type checks.
Local real-model validation uses OPT-125m, Qwen3-0.6B, and Qwen3.5-0.8B. GPU cache capacity is constrained and cache residency layouts are controlled to trigger actual CPU loads. Validation compares cold-cache and warm-cache outputs under deterministic generation settings and checks transfer positions and reference cleanup.
Test Result
After the October 30 merge with upstream main (
dfe4d99e42):Additional regression command:
The three missing-config streaming cases were rerun after fetching
Qwen/Qwen3-Next-80B-A3B-Instruct/config.json. The three hardware-limited cases were reproduced in a separate worktree at upstream main. The real-model smoke test used GCC because the machine's default Clang is unsupported by the installed CUDA compiler.Earlier, 22 model/configuration combinations passed with 9,146 exact cold/warm comparisons; that full matrix has not been rerun after this merge. Some earlier OPT/MTP cold/warm differences also reproduced on the legacy lookup path and are excluded from the passing results.
AI assistance
GPT-6 Astra assisted with the implementation, tests, and this description. The code has undergone human review.
Codex also assisted with the October 30 merge resolution and validation.