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[ROCm] Add head-fused HIP sparse MLA decode kernel for gfx950 - #57282
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Single-kernel sparse MLA decode that groups MQA heads (HG=2) so each token's KV latent is loaded ONCE and reused across heads, cutting KV read traffic ~2x vs the per-head Triton path. Targets the DSpark spec-decode batch range B=33-72 (C=8 → B=48). Microbench (rocprofv3, MI355X gfx950): B=48: M5 9.9µs vs Triton 12.4µs (1.25x) vs M4 11.0µs SNR: 51.77 dB E2e agentx bench (3600s, C=8, TP=4, MTP spec-decode): P90 interactivity: 139.5 → 146.6 tok/s/user (+5.1%) P90 TTFT: 1.067s → 0.970s (−9.1%) Output tok/s/chip: 93.0 → 93.7 (+0.8%) Gated behind VLLM_ROCM_USE_HIP_SPARSE_MLA=1 env var. Kernel .so path configurable via VLLM_ROCM_HIP_SPARSE_MLA_M5_SO. HIP source included at csrc/rocm/mla/sparse_mla_decode_m5.hip. Build: hipcc -x hip --offload-arch=gfx950 -O3 -std=c++17 -fPIC -shared Co-Authored-By: Claude <noreply@anthropic.com>
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Purpose
Add head-fused HIP sparse MLA decode kernel for MI355X (gfx950). The kernel groups MQA heads (HG=2) so each token's KV latent is loaded once and reused across heads, cutting KV read traffic ~2x vs the per-head Triton path. Targets DSpark spec-decode batch range B=33-72 (C=8 → B=48 for DeepSeek-V4.1-Flash).
Gated behind
VLLM_ROCM_USE_HIP_SPARSE_MLA=1env var — opt-in, zero impact when disabled. Falls through to existing Triton ragged decode outside the dispatch range.Test Plan
hipcc -x hip --offload-arch=gfx950 -O3 -std=c++17 -fPIC -shared csrc/rocm/mla/sparse_mla_decode_m5.hip -o libsmla_m5.soVLLM_ROCM_USE_HIP_SPARSE_MLA=1 VLLM_ROCM_HIP_SPARSE_MLA_M5_SO=<path>/libsmla_m5.soTest Result
Microbench (rocprofv3, MI355X gfx950):
SNR vs Triton reference: 51.77 dB at B=48.
E2E (agentx, 3600s, C=8, TP=4, MTP spec-decode, DeepSeek-V4.1-Flash, MI355X):
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