[Model] Fix DeepSeek-V4.1-Flash SM120/GB10 geometry mismatch for SWA …

[zeenat28-ui]

Fixes #56461.

Summary

On SM120 and SM121 architectures (such as GB10), DeepGEMM kernels enforce a strict hardware invariant: the number of kernel states (num_states) must equal 64.

For DeepSeek-V4.1-Flash, this created a geometry mismatch because the SWA cache layer block size was hardcoded to 32, and the indexer backend attempted unsupported virtual block splitting between ratio-1 and ratio-2 layers. This PR aligns the block size geometry across SWA and indexer backends on SM120/SM121 to satisfy the DeepGEMM requirement without altering the behavior on older architectures.

Hardware and Kernel Context

• DeepGEMM SM120 kernel constraint: num_states == 64.
• For ratio-1 layers (tokens_per_state == 1): requires kernel_block_size == 64 to yield 64 states.
• For ratio-2 layers (tokens_per_state == 2): requires kernel_block_size == 128 to yield 64 states (128 // 2 == 64).
• SWA sliding-window cache: aligned to block size 64 on SM120/121 so paged attention allocations match the indexer's kernel state geometry.

Changes

• SWA block size resolution (vllm/models/deepseek_v41/attention.py):
  Checks platform capability family and selects block size 64 for SM120 and SM121, falling back to 32 when the platform is unavailable or on other architectures. Uses kv_cache_spec.get_num_kernel_states to guard against zero compression ratios.

• Indexer backend (vllm/v1/attention/backends/mla/indexer.py):
  Exposes [64, 128] on SM120/SM121 instead of forcing [128, 64], allowing both ratio-1 and ratio-2 layers to take their required spec size directly without virtual block splitting. Added explicit layout guards naming packed and strided layouts.

• Backend capability declarations:
  Updated vllm/models/deepseek_v41/sparse_mla.py and vllm/models/deepseek_v41/nvidia/flashinfer_sparse.py to declare block size 64 support on SM120/SM121.

• Regression tests (tests/v1/attention/test_deepseek_v41_block_size.py):
  Added comprehensive tests covering block size selection across SM90, SM120, and SM121, verifying ratio-1, ratio-2, and common-size resolution paths.

Validation

• ruff check: All checks passed with 0 errors.
• ruff format: Compliant with the 88-character limit across all touched files.
• pytest: Verified test suite passes cleanly.

[claude]

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[zeenat28-ui]

@pavanimajety Hello! Could someone please review this PR and add the ready or verified label to unblock the pre-commit checks? Thank you!

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[simon-lee-dev]

Hardware validation on SM120 (8× RTX PRO 6000D): this PR is necessary but not sufficient

Tested on real SM120 hardware, which the PR description notes was not available:

• GPUs: 8× NVIDIA RTX PRO 6000D (sm_120, 83.05 GiB usable each), TP=8, PCIe (no NVLink)
• Image: vllm/vllm-openai:deepseekv41-flash-0909
• Model: deepseek-ai/DeepSeek-V4.1-Flash (475.3 GiB, MXFP4 experts + MXFP8)

Applying the 4 changes in this PR verbatim, startup still fails during CUDA graph capture:

RuntimeError: Assertion error (csrc/apis/attention.hpp:320):
  (arch_major == 10 and (block_kv == 32 or block_kv == 64 or block_kv == 128))
  or (arch_major == 9 and (block_kv == 32 or block_kv == 64))
  or (arch_major == 12 and ((is_fp4 and (block_kv == 32 or block_kv == 64))
                            or (not is_fp4 and block_kv == 64)))

Why ratio-1-only is not enough

DeepseekV4IndexerCache.get_kv_cache_spec() builds MLAAttentionSpec(block_size=cache_config.block_size, tokens_per_state=compress_ratio), and num_states = block_size // tokens_per_state is what reaches get_paged_mqa_logits_metadata(). The indexer K cache is FP8 here (is_fp4=False), so arch 12 accepts only 64.

DeepSeek-V4.1-Flash's config.json has compress_ratios containing only {0, 1, 2} (18 layers at 2, 20 at 1). So a single global block size cannot satisfy both:

spec.block_size	ratio-1 layers	ratio-2 layers
64	num_states=64 ✅	num_states=32 ❌
128	num_states=128 ❌	num_states=64 ✅

This PR's [64] fixes the ratio-1 layers (matching its description: "return 64 on ratio-1 layers"), but the 18 ratio-2 layers still yield 32 and trip the assertion.

What made it work

Two additional changes on top of this PR:

1. Scale the indexer spec block size by the layer's compression ratio, so both kinds land on num_states == 64:

   # DeepseekV4IndexerCache.get_kv_cache_spec
   block_size=self.cache_config.block_size * max(1, self.compress_ratio)

2. Have DeepseekV41IndexerBackend.get_supported_kernel_block_sizes() return [64, 128] on families 120/121, not [64].

Step 2 is required because with only [64] declared, select_common_block_size() falls to case 2 and tries to split the 128-token manager block into 2×64 kernel blocks, which this model's available layouts cannot do:

The resolved KV cache layout (BLHNC) does not store blocks as dense, unpadded pages
(block stride 103104 != page 8448), so a manager block cannot be split into 2 kernel
blocks of 64 tokens. ... set VLLM_KV_CACHE_LAYOUT to a layer-compact layout (e.g. LBNHC).

LBNHC is not selectable for this model (valid layouts: ['BLHNC', 'BLNHC']), so avoiding the split is the practical route. Declaring both sizes lets each group take its spec size directly (case 1), no split. A side benefit is that both groups end up with equal page sizes (num_heads × num_states × state_bytes).

Also worth noting: routing the indexer to MXFP4 (which would make block_kv=32 legal per the assertion) is explicitly gated off — dsa_indexer_uses_fp4() raises indexer_kv_dtype='mxfp4' requires Blackwell datacenter GPUs (sm_10x).

Separately: flashinfer needs topk=1152 instantiations

Not in scope for this PR, but required to reach a running server on SM120. DeepSeek-V4.1-Flash derives topk=1152 (1024 compressed + 128 sliding window), which is not instantiated in the SM120 kernels:

• _DECODE_DSV4_DISPATCH / sparse_mla_sm120_decode_dsv4.cu: only topk ∈ {128,192,256,512,1024}
• sparse_mla_sm120_prefill.cu, single-cache path: only {128,192,256,512,1024,2048}
• sparse_mla_sm120_prefill.cu, dual-cache path: hardcoded to BF16/topk=128, and extra_page_block_size ∈ {64, 2} — V4.1 calls it with topk=1152, topk_extra=512, extra_page_block_size=32

Adding those instantiations looks safe rather than a redesign: DYN_SMEM_BYTES in the decode launcher does not depend on TOPK (fixed ~89 KB, under the 100 KB SM120 carveout), TOPK appears only as a scalar clamp and an indices stride inside the kernel, 2048 is already instantiated on the single-cache prefill path, and page block size only participates in page-index arithmetic (the dual path already runs a runtime pbs_extra=2).

Result

With this PR plus the two changes above plus the flashinfer instantiations, the server reaches Application startup complete and serves correctly:

per-GPU memory	76.4 GiB (78239 MiB) at --gpu-memory-utilization 0.92
KV cache	731,383 tokens
max concurrency @ 32K	22.32x
single-stream decode	77.5 / 79.5 / 80.1 tok/s
prefill	4,559-token prompt + 80 output tokens in 1.6 s total
correctness	spot-checked reasoning/arithmetic answers correct

Config used: --tensor-parallel-size 8 --enable-expert-parallel --max-model-len 32768 --engram-config '{"cpu_offload": false}'. (cpu_offload: true, the default, needs ~188.8 GiB of pinned host memory for the two Engram tables — 11.80 GiB per rank per table — which OOM-kills a 251 GB host.)

Happy to test revisions of this PR on the same hardware if that helps.

[simon-lee-dev]

The two additions in the latest push match the implementation I validated on sm_120 hardware and described in my earlier comment: the per-layer cache_config.block_size * compress_ratio for the indexer spec, and declaring [64, 128] on SM120/121. With both in place the DeepGEMM arch_major == 12 assertion no longer triggers on the ratio-2 layers.

num_states = kernel_block_size // self.compress_ratio is equivalent to the spec.num_states I ran with whenever a group's kernel block size equals its spec block size (ratio-1: 64//1, ratio-2: 128//2, both 64), and it is the more correct form if the two ever diverge.

One question about the new block_factor > 1 path, specifically the comment "This is needed for ratio-1 layers on SM12x too". DeepseekV4IndexerBackend.supported_kv_cache_layouts is (BLHNC, BLNHC) — the layer dim sits inside the block dim, so a manager block is not a dense, unpadded page. flat_kv_row_view in vllm/v1/kv_cache_interface.py rejects exactly that combination:

The resolved KV cache layout (...) does not store blocks as dense, unpadded pages (block stride X != page Y), so a manager block cannot be split into N kernel blocks of M tokens.

Declaring [64, 128] is what lets each KV cache group select its own spec size directly, so block_factor stays 1 and no split is attempted. If some configuration does reach block_factor > 1 on SM12x, I would expect either that ValueError, or — if the tensor view is not subdivided in lockstep with the builder-side block_table[:, ::block_factor] // block_factor — silently wrong page indexing, which is the worse outcome. Is there a configuration where ratio-1 genuinely needs the split? If not, an explicit guard or assert may be safer than the general path.

For anyone landing here from #56461: this PR covers two of the three distinct failures in that issue. The third one (top-k 1152 not instantiated in the FlashInfer sparse-MLA kernels) is independent of page geometry — see #56623 and flashinfer-ai/flashinfer#5174.

[zeenat28-ui]

You're right sir, ratio-1 doesn't need the split. I've replaced the old block-split fallback with an explicit ValueError guard..if any other issue happens, please mention..

[simon-lee-dev]

Thanks — the explicit guard reads correctly, and the error message naming the packed/strided layouts is much clearer than a split that fails deeper in.

One thing to double check in the same hunk: kernel_block_size // self.compress_ratio divides by zero when compress_ratio == 0. In the builder, self.compress_ratio is assigned straight from kv_cache_spec.tokens_per_state, and upstream treats zero as a valid value — MLAAttentionSpec.get_num_kernel_states() guards it explicitly:

def get_num_kernel_states(self, kernel_block_size: int) -> int:
    if self.tokens_per_state > 0:
        return kernel_block_size // self.tokens_per_state
    return 1

That is also why block_size=self.cache_config.block_size * max(1, self.compress_ratio) needs its max(1, ...) in attention.py.

Using the existing helper instead of open-coding the division keeps that guard and expresses the intent directly:

self.kv_cache_spec.get_num_kernel_states(kernel_block_size)

It returns exactly the value you want in both call sites (ratio-1: 64 // 1, ratio-2: 128 // 2), and it stays correct if the kernel block size and the spec block size ever diverge.

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[bluemelov1]

Independent data point from RTX PRO 6000 Blackwell (sm_120, 8× PCIe, no NVLink), DeepSeek-V4.1-Flash TP8.

We hit the same No common block size failure and patched it independently before finding this PR, with the same decision: each compression ratio gets its own spec block size (ratio 1 → 64, ratio 2 → 128), so the kernel sees num_states == 64 without virtual splitting. Two properties we checked before relying on it:

• both ratios yield the same page size (37,440 B per block in our config), so the shared pool still sees uniform pages;
• hash_block_size resolves to gcd = 64.

With that we serve in production at 1,075 output tok/s at 32 concurrent and 1,481 at 64, 128k context; needle retrieval 9/9 (1.5k/12k/37k prompts × 3 depths, no decoy hits).

Note: we ran our own patch, not this branch. Main has since moved the indexer to [256], so this needs a rebase. Happy to test the rebased branch on this hardware.

[zeenat28-ui]

@bluemelov1 thanks for sharing the production benchmarks and validation on RTX PRO 6000 (sm_120)!
I've rebased the branch onto the latest main. Would really appreciate it if you could test this rebased branch on your cluster whenever you get a chance!

[simon-lee-dev]

Second sm_120 data point, independent of @bluemelov1's.

Hardware: 8× RTX PRO 6000D (sm_120, PCIe, no NVLink), DeepSeek-V4.1-Flash TP=8, 128K context, gpu_memory_utilization=0.92, max_num_seqs=32, DSpark on.

Scope — please read this before weighting the result. We did not build the rebased branch against current main. Our base is a pinned vLLM build from Sept 9 that predates the deepseek_v4_1 → deepseek_v41 rename, so dropping the rebased files in wholesale would have pulled in ~2 weeks of unrelated main drift (indexer.py is 1785 lines on the branch vs 1430 on our base, 693 lines differing) and any failure would have been unattributable. Instead we isolated the part of this PR that differs from the patch set we have been running in production since 2026-09-14 — the build() rewrite in indexer.py:

• hoisting kernel_block_size = self.kernel_block_size or self.kv_cache_spec.block_size
• replacing the silent virtual-split path with the explicit ValueErrors
• both kv_cache_spec.num_states call sites → get_num_kernel_states(kernel_block_size)

The other four changes in this PR are semantically what we already run; that half we validated on 2026-09-14.

Result: identical geometry, no regression.

	our existing patches	this PR's build() delta
KV cache @128k	1,539,389 tokens / 11.74x	1,539,389 tokens / 11.7x
single stream	137–141 tok/s	130.8 tok/s
8-way aggregate	560 tok/s	562 tok/s
startup errors	0	0

Functional checks pass: arithmetic (13² + 84² = 7225 = 85²), Chinese generation, tool calling (get_weather({"city": "杭州"})), and reasoning field separation.

One observation worth recording: the new Virtual block splitting guard never fires. With [64, 128] declared for sm_120 plus block_size * max(1, compress_ratio), storage and kernel block size are already equal per KV group (block_factor == 1), so turning this into a hard error does not cut off a working path on this hardware. That is consistent with @bluemelov1's check that both ratios land on the same page size.

Also good to see the ratio-2 half we reported on 2026-09-14 now carries a unit test (test_indexer_spec_scales_block_size_for_compression).

Still unverified from our side: whether the rebased branch integrates with current main. That needs someone building against main; we cannot speak to it.

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[bluemelov1]

Tested the rebased branch (ad210a8) on 8× RTX PRO 6000 Blackwell (sm_120, PCIe, no NVLink), DeepSeek-V4.1-Flash, TP8.

Build. ad210a8 sits on 157bcb7 (#56956). I used vllm/vllm-openai:nightly-e9757321527ca1ecd514c07c1418dd2c53da3d19. That image is 23 commits before the merge base, but none of those commits touch the four files this PR changes: their sha256 in the image matches 157bcb7. I copied the four files from ad210a8 over the image: models/deepseek_v41/attention.py, models/deepseek_v41/nvidia/flashinfer_sparse.py, models/deepseek_v41/sparse_mla.py, v1/attention/backends/mla/indexer.py. FlashInfer is 0.6.18.post1. The newer nightly already contains #53175, which changed get_supported_kernel_block_sizes(kv_cache_spec=None) in these same files. That is probably the current conflict.

Flags. --tensor-parallel-size 8 --language-model-only --max-model-len 131072 --max-num-seqs 64 --max-num-batched-tokens 8192 --enable-chunked-prefill --enable-prefix-caching --engram-config '{"cpu_offload": false}', deepseek_v41 tokenizer and reasoning parser, VLLM_USE_RUST_FRONTEND=1. Default compilation (FULL + PIECEWISE graphs).

The PR's unit tests pass: 19/19 in the image.

1. Branch as-is, DSpark off: fails in warmup. Global block becomes 64 as intended, and weights and KV allocate. The first dummy prefill in compile_or_warm_up_model then dies:

[interface.py:621] Setting kv cache block size to 64 for FLASHINFER_MLA_SPARSE_DSV41 backend.
[kv_cache_utils.py:2432] GPU KV cache size: 1,976,371 tokens, Maximum concurrency for 131,072 tokens per request: 15.08x
...
  File ".../models/deepseek_v41/nvidia/flashinfer_sparse.py", line 959, in _forward_prefill
tvm.error.InternalError: Check failed: (ok) is false: Unsupported sparse-MLA prefill configuration:
model=DSV4 num_heads=8 topk=128 page_block_size=64 topk_extra=512 extra_page_block_size=32

extra_page_block_size=32 is the compressed-KV cache of the ratio-2 kv-source layers. The PR scales the indexer spec per ratio (DeepseekV4IndexerCache.get_kv_cache_spec: block_size * max(1, compress_ratio)). The compressed-KV spec in DeepseekV4Attention.get_kv_cache_spec still uses vllm_config.cache_config.block_size. At a global block of 64, ratio-2 layers therefore get 64 tokens = 32 states per page, and the SM120 prefill kernel only accepts 64 states. This checkpoint has compressed-KV sources at both ratios, so the ratio-1 and ratio-2 layers need different token block sizes, the same as the indexer. The KV size shows it too: 11.95 GiB / 1,976,371 tokens = 6,492 B/token, against 7,066 once the spec is fixed (below).

2. Branch + a 2-line follow-up, DSpark off: serves and passes. The follow-up does the same thing for the compressed-KV spec that the PR does for the indexer:

--- a/vllm/models/deepseek_v41/attention.py
+++ b/vllm/models/deepseek_v41/attention.py
@@ DeepseekV4Attention.get_kv_cache_spec
         return MLAAttentionSpec(
-            block_size=vllm_config.cache_config.block_size,
+            block_size=vllm_config.cache_config.block_size * max(1, self.compress_ratio),
--- a/vllm/models/deepseek_v41/nvidia/flashinfer_sparse.py
+++ b/vllm/models/deepseek_v41/nvidia/flashinfer_sparse.py
@@ DeepseekV4FlashInferMLASparseBackend.get_supported_kernel_block_sizes
         ) or current_platform.is_device_capability_family(121):
-            return [64]
+            return [64, 128]

The global block stays 64, because get_preferred_block_size still picks the minimum. Each group then negotiates kernel block = storage block: ratio 1 at 64/64, ratio 2 at 128/128. I did not test the spec change without the [64, 128] line. Result: ready in 7 m 23 s, 11.95 GiB KV/rank, 1,815,989 tokens.

Correctness gate:

• needle-in-a-haystack 9/9 (1.6k / 12k / 35.6k-token prompts × 3 depths, no decoys);
• greedy 3×3 identical and correct;
• divergent continuations over a shared prefix correct.

The new "Virtual block splitting" guard never fired.

3. Branch + follow-up + #58560, DSpark on (num_speculative_tokens 5), FULL graphs: serves and passes. Same gate, 0 Xid. Ready in 9 m 33 s, 8.22 GiB KV/rank, 1,202,837 tokens. DSpark acceptance is 0.38 at every level (mean length 2.9). On sm_120, DSpark + FULL graphs also needs #58560 (#58560). Without it, the compressor ring writes into the KV null block during warmup, and the SM120 sparse decode later reads that block. We saw Xid 31 MMU faults on the first real request. That is unrelated to this PR. I did not re-run it here.

Output tok/s, unique ~2.3k-token prompts, 512 output tokens, greedy, 150 s per level, 0 errors:

concurrency	2. DSpark off	3. DSpark on	TTFT p50 / p99 (3.)	TPOT p50 (3.)
1	49.7	115.1	0.26 / 0.27 s	8.2 ms
4	218.1	331.4	0.29 / 0.86 s	11.4 ms
16	542.0	677.0	0.50 / 3.07 s	22.3 ms
32	751.8	873.7	0.59 / 6.05 s	34.5 ms

N per level: 15 / 64 / 160 / 224 (DSpark off) and 34 / 100 / 208 / 274 (DSpark on). Client and engine token counters agree within 0.5 %. The DSpark-on numbers match our earlier v0.30.0 runs of the same geometry (c16 670). The remaining gap to our patched build is a separate DeepGEMM MoE alignment issue on SM120, not this PR.

Summary:

• On sm_120 TP8, the branch as-is does not start DeepSeek-V4.1-Flash.
• The SWA page of 64, the per-ratio indexer spec and the [64, 128] indexer kernel sizes work. The compressed-KV spec also needs the per-ratio block size, together with [64, 128] on the FlashInfer sparse backend.
• With those two lines added, text-only serving is correct, with DSpark off and with DSpark on plus [Bugfix][DSv4.1] Keep the compressor ring out of the null block #58560.
• A startup check that states-per-page equals 64 on every compressed spec would turn this into an init error with a clear reason, instead of a kernel check failure in warmup.

[zeenat28-ui]

Thanks a lot @bluemelov1 and @simon-lee-dev for the thorough real-hardware validation and detailed diagnostics on Blackwell (sm_120)! have rebased onto the latest main (resolving the #53175 conflict), scaled the compressed-KV block_size by compress_ratio, and declared [64, 128] on the FlashInfer backend. I also added the startup check you suggested alongside regression unit tests so it fails fast if geometries ever misalign.
Good to know it runs cleanly with #58560 on top for DSpark,really appreciate your help in getting this verified and sorted!