[Multimodal] Add TorchCodec device option (CUDA/NVDEC decode) with host-frame conversion

[arif-ahmed-nv]

Purpose

TorchCodec can decode on the GPU with NVDEC (VideoDecoder(..., device="cuda")) when the installed build has CUDA support, but the vLLM torchcodec video backend never forwards a device, so GPU decoding cannot be selected through --media-io-kwargs. Its CUDA output tensors also cannot be converted to NumPy directly, which is what the multimodal processors consume.

This PR adds an opt-in, TorchCodec-only device option:

• Register device (default None) with the torchcodec backend defaults so the existing backend-kwargs validator accepts it for torchcodec and rejects it for other backends.
• Forward it to VideoDecoder only when set, so the CPU default and TorchCodec's own device validation are untouched.
• Copy only the sampled frames to the host (batch.data.cpu().numpy()) before the NumPy conversion. This is a no-op for the CPU decoder.
• Treat backend=torchcodec, device=cuda as a GPU video backend in MultiModalConfig.use_gpu_video_backend(), so the frontend GPU memory reservation added for PyNvVideoCodec applies, and account the sampled frames against the --mm-ipc-gpu-memory-gb pool (get_mm_gpu_ipc_pool().acquire(...)) like the other GPU backends.
• Document the option, reuse the existing CUDA MPS / reservation guidance, and add unit tests plus a CUDA-gated frame-correctness test against the CPU decoder.

Why this is useful upstream:

• Video decoding runs in the API server process. With the CPU backends a single 1080p or 4K request pins several cores, so the frontend becomes CPU-bound under concurrent video traffic before the GPU is busy. NVDEC is fixed-function hardware that does not compete with the model for SMs. In the measurements below GPU decode uses roughly 20x less API-server CPU and gives higher throughput at concurrency 8, at the cost of higher single-request latency (decoder setup plus the device-to-host copy).
• It reuses a dependency vLLM already supports (TorchCodec) rather than adding a vendor-specific one, and the CUDA output matches the default OpenCV path within a mean absolute error of 0.4 (uint8), so switching does not change what the model sees.
• Off by default. Existing users see no change.
• Systems with few CPU cores per GPU (for example DGX Spark class machines) benefit the most, but nothing here is platform specific.

Related: #30839 (RFC: zero-copy video with PyNvVideoCodec and IPC) introduced the frontend GPU memory pool this change hooks into.

Not in scope, possible follow-ups: keeping decoded frames on the GPU through preprocessing (frames are still copied to host here), reusing a decoder across requests (most of the single-request latency gap), and NVDEC codec-coverage fallbacks. device="cuda" requires a CUDA-enabled TorchCodec build; other builds keep the CPU default.

Test Plan

Unit tests (CPU; the CUDA-vs-CPU frame test runs only when CUDA and a CUDA TorchCodec build are available):

pytest tests/multimodal/test_video.py -k "torchcodec or backend_kwargs or device or lazy_imported or decoder_spec"
pytest tests/multimodal/test_gpu_ipc_memory.py
pytest tests/config/test_multimodal_config.py -k gpu_video_backend

Correctness and benchmark harness (synthetic H.264 clips generated with ffmpeg testsrc2, 1080p and 4K, 10 s at 30 fps, GOP 60; 8 and 32 sampled frames; concurrency 1 and 8; 5 rounds; sampled frames compared against the OpenCV reference decode):
https://github.com/arif-ahmed-nv/vllm-windows/tree/bench/video-decode

Environment: 1x H100 SXM (DGX Cloud Lepton), driver 570.195.03 with the CUDA 13 forward-compatibility package, torch 2.13.0+cu130, torchcodec 0.16.0+cu130, ffmpeg 6.1 (Ubuntu 24.04). Two runs of the unit tests and the correctness check: first on the original base (c7e6e36) with this branch installed as a precompiled editable build (VLLM_USE_PRECOMPILED=1), then again on the rebased head (32f4bd0 on top of main ae71862; the rebase onto ae71862 touched none of the changed files, and the only code change after the second run is a type annotation for mypy) installed as a Python-only editable build over the compiled libraries of nightly 0.28.1rc1.dev614+g26fec6d18. The benchmarks below are from the first environment.

Test Result

Unit tests, identical on both runs: tests/multimodal/test_video.py 20 passed, 0 skipped (including the CUDA-gated test_torchcodec_cuda_backend_matches_cpu_frames), tests/multimodal/test_gpu_ipc_memory.py 18 passed, tests/config/test_multimodal_config.py 6 passed.

Frame correctness, torchcodec + device=cuda vs OpenCV reference, 8 sampled frames, identical on both runs: matching frame indices and shapes on every clip (1080p, 4K, 720p); mean absolute error 0.401 / 0.401 / 0.342 (uint8), p99 absolute difference 2, max 2.

Decode benchmark, 8 sampled frames per request, 5 rounds, conc = concurrent requests decoding in one process. The container's CPU quota was about 20 cores (CPU decode plateaus there), so the concurrency 16 rows show the CPU-bound regime.

clip	backend	p50 ms, conc 1	p50 ms, conc 8	p50 ms, conc 16	frames/s, conc 8	frames/s, conc 16	avg CPU cores (conc 1 / 8 / 16)	process GPU MiB (conc 1 / 8 / 16)
1080p	opencv	199	1052	2354	57.4	50.9	9.6 / 19.6 / 19.8	0
1080p	torchcodec (cpu)	158	782	2379	80.5	52.9	8.4 / 20.0 / 19.8	0
1080p	torchcodec device=cuda	374	551	1034	88.1	100.2	0.19 / 1.16 / 1.42	690 / 1229 / 1846
4K	opencv	704	4685	12416	13.2	9.8	11.6 / 19.7 / 19.9	0
4K	torchcodec (cpu)	553	3592	10529	17.6	12.2	9.6 / 19.6 / 19.8	0
4K	torchcodec device=cuda	1222	1867	3495	26.3	28.7	0.17 / 0.80 / 0.92	2120 / 3932 / 5905

Notes:

• With 20 cores available, single-request latency is higher on CUDA (decoder and CUDA context setup, plus the device-to-host copy of the sampled frames). Under concurrency the CPU backends saturate the available cores and their throughput falls as concurrency grows, while CUDA decode keeps scaling: at concurrency 16, 1.9x the frames/s of TorchCodec CPU at 1080p and 2.4x at 4K, with 2.3x to 3x lower request latency, using about 1 core instead of 20. This is a CPU-offload and scaling option, not a single-request latency optimization.
• Process GPU memory grows with resolution, frame count, and concurrency, reaching about 9.5 GiB in the worst case measured earlier (4K, 32 frames, concurrency 8). The reservation added here makes the engine account for it, and --mm-ipc-gpu-memory-gb bounds it.

CPU-constrained hosts. Same benchmark with the decoding process pinned (taskset) to 8 and to 4 cores, which is closer to the per-GPU CPU share on dense GPU nodes and on small systems such as DGX Spark. CUDA decode is unaffected by the pin (within noise of the 20-core numbers above); the CPU backends slow down proportionally.

cores	clip	conc	opencv p50 ms / frames/s	torchcodec (cpu) p50 ms / frames/s	torchcodec device=cuda p50 ms / frames/s	CUDA vs TorchCodec CPU
8	1080p	1	302 / 26.3	235 / 33.8	371 / 21.4	1.6x slower
8	1080p	16	3450 / 35.8	2413 / 51.7	1020 / 100.6	2.4x faster, 1.9x throughput
8	4K	1	1140 / 7.0	795 / 10.0	1217 / 6.5	1.5x slower
8	4K	16	14822 / 8.3	9542 / 13.2	3464 / 28.9	2.8x faster, 2.2x throughput
4	1080p	1	486 / 16.4	375 / 21.0	371 / 21.4	parity
4	1080p	16	6673 / 18.6	4520 / 27.8	1010 / 99.0	4.5x faster, 3.6x throughput
4	4K	1	1956 / 4.1	1316 / 6.1	1218 / 6.5	1.1x faster
4	4K	16	29796 / 4.2	17564 / 7.2	3502 / 28.1	5.0x faster, 3.9x throughput

CPU used by the decoding process in these runs: 7.8 to 8.0 cores (8-core pin) and 3.9 to 4.0 cores (4-core pin) for both CPU backends at concurrency 8 and 16, versus 0.8 to 1.2 cores for CUDA decode. Process GPU memory for CUDA decode was identical to the 20-core runs (690 to 1846 MiB at 1080p, 2120 to 5905 MiB at 4K for 8 frames).

[mergify]

Documentation preview: https://vllm--56333.org.readthedocs.build/en/56333/

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[arif-ahmed-nv]

Closing: #53675 (merged today) adds the TorchCodec device option this PR proposed, keeping decoded frames on the GPU for encode-only EPD instances, so the core of this change is now upstream.

What is not covered there is the regular single-instance case with a CPU-side processor: device=cuda is not counted in the frontend GPU memory reservation, and the CUDA frames flow into the HF processor without a host copy. I will follow up separately on that, with the H100 measurements from this description, once the preferred direction is clear (forbid device=cuda off encode-only instances, or account for it and convert frames to host when the processor runs on CPU).