[Kernel] Fuse MiniMax M3 common decode top-k merge

[venkywonka]

Current candidate: 32bdcb11ee4a7f8bc1c517d05d92b12ff67d7dca, based on pinned upstream c1b69aa0d49b88016b5b2156ae61649c2c2df282. The branch history was preserved through a merge. The delta against that base changes only the common top-k kernel and its existing test file.

This provides common/CUDA backend coverage for the last-arriving-CTA merge approach already implemented for AMD in merged #54682; algorithmic novelty is not claimed. The common comparison network and per-call counter ownership are retained. The latest cleanup gives the fused kernel an accurate name and strengthens tied-cutoff validity checks; it adds no dispatch policy or performance claim.

At this head, scoped pre-commit (including mypy) and five CPU checks of the test's tied-cutoff oracle passed. Native GPU, candidate model/GSM8K, matched serving, and combined-stack validation have not run at this head. All GPU results below apply only to historical head 70fc451a5e against source 8c87c333. A fresh c1 baseline and coherent runtime are required. The prior ten timing cells contained six wins, three small stable losses and one inconclusive result; launch reduction alone is not an unconditional performance win.

The standalone delta remains compatible with the pinned base. Series integration follows #49229/grid, #56150/prefill scorer, then this fusion, with the final actual producer count shared by partial buffers, arrival threshold and merge width. Combined integration is coordinator-owned.

Human line-by-line review and human-run relevant tests are not verified. This remains a draft, with further source publication held until that gate is explicitly satisfied. Shared-baseline or compound-stack evidence is not individual candidate qualification.

Historical implementation and validation notes at 70fc451 / base8c87c333

MiniMax M3's common decode indexer launches separate partial top-k and merge
kernels. Perform the existing merge in the last arriving partial CTA instead,
reducing score-plus-selection from three kernel launches to two. Each call
owns its counter scratch; the score kernel initializes it, and the fused tail
resets it so repeated tuning launches and graph replays can reuse it safely.

The bitonic comparison network, candidate ordering, NaN/padding handling,
forced block scores, and grid constants are preserved. Added tests cover
poisoned counter initialization/reset, strided buffers, NaNs, forced blocks,
padded requests, concurrent calls, and independent CUDA graph replay.

This is distinct from merged #54682 and open #55235/#53448, whose selector
changes concern the AMD implementation. #53448's common kernel-file change
only adds a dtype declaration. #49229 owns separate grid tuning. Duplicate
searches, the linked AMD issue #54681, and the exact fork/head were rechecked
on 2026-09-09 before draft publication; no common/CUDA merge owner or existing
PR from this fork/head was found.

Rebased onto main 8c87c333b84c85908b1d11f0044457692277c6f3; both changed
files are byte-identical to the previously validated patch. The following
checks were rerun on the rebased head using an RTX A5000, Python 3.12.13,
PyTorch 2.13.0+cu130 and Triton 3.7.1. The retained editable environment uses
native artifacts from c69d5d72a6018db6ff55efc66097d377c25828cc; no native
source changed between these bases. It retains FlashInfer 0.6.18 while the new
base requires 0.6.18.post1; these common Triton tests do not exercise that
backend. This is focused validation, not full new-base dependency/model
qualification:

CUDA_VISIBLE_DEVICES=1 .venv/bin/python -m pytest \
  tests/kernels/attention/test_minimax_m3.py -q \
  -k '(decode_index_topk or prefill_index_topk) and not amd'
# Post-rebase: 11 passed, 2 skipped in 7.81 s (existing SM100-only FP8 tests).

.venv/bin/python -m pre_commit run --files \
  vllm/models/minimax_m3/common/ops/index_topk.py \
  tests/kernels/attention/test_minimax_m3.py
# Post-rebase: all applicable hooks passed, including mypy.

Before rebase, a local harness also passed 300 exact ordered-ID comparisons
against the pinned two-launch implementation, spanning every existing autotune config,
chunk counts 1/2/4/8/16, top-k 6/16, ties, NaNs, padding, and forced scores.
Counters were checked at zero after repeated launches without rescoring.
This is matched-configuration parity: the inherited comparator can choose
different tied IDs across tile widths, and fusion can change the autotune
winner. No universal tie-order or model-output equivalence is claimed.

All 44 offline SM120/PDL specializations compiled with the expected emitted
memory-ordering sequence. A local preview with #49229's grid constants passed
five producer-count/correctness cases. Profiling measured three -> two CUDA
kernels without a fill launch. Nine public-wrapper comparisons also matched
ordered IDs with unconstrained autotuning in this run. A5000 CUPTI graph
measurements were mixed and close to parity; an unstable baseline outlier is
excluded from speedup claims. No consistent performance improvement is claimed
from those measurements.

Austin SM120/PDL correctness, memcheck, and initial standalone performance results are recorded below. Focused timing confirmation and MiniMax model/GSM8K evaluation remain pending. No model-evaluation result or whole-recipe speedup is claimed. This PR is intentionally a draft for human
review. Human review of every changed line, relevant tests, and the remaining
performance and model validation are required before marking it ready for review.
Human review and unexecuted validation are not claimed as completed.

AI assistance was used for implementation, tests, source comparison, and
review (GPT-6 Astra, xhigh reasoning).

Actual Austin RTX PRO 6000 Blackwell (SM120) validation at 70fc451a5e367d05a0121441247402e7d470d2d6, base 8c87c333b84c85908b1d11f0044457692277c6f3:

• Container coherence passed: all 6,983 tracked files and all 17 native libraries match the source/wheel records; Torch 2.13.0+cu130, Triton 3.7.1, FlashInfer 0.6.18.post1. Native CUDA operator health and graph replay passed.
• 660 native checks passed in 955.8 s: 200 baseline PDL/control ordered comparisons, 400 matched-configuration fused ordered-ID/counter-reset checks with real PDL consumers, 50 cross-configuration tie-validity checks, and 10 pytest cases passed, 0 failed, 0 skipped. NaN/sentinel cases match inherited baseline behavior; tied finite-score cases require complete valid unique IDs and equal selected-score multisets.
• All 400 matched-configuration ordered-ID comparisons passed. Across different tile/chunk configurations, 46/50 deliberate tied-cutoff cases selected different valid equal-score ID sets and 4/50 matched exact ordering. These are separate claims.
• Compute Sanitizer memcheck: 4 passed, 0 failed, 0 skipped, 130 deselected in 80.10 s; 0 memory errors. This separate follow-up repeated native health and exercised the published NaN/forced-block/strided-buffer/reset and concurrent-call/independent-graph tests using CUDA sanitizer component 13.0.85 (Compute Sanitizer 2025.3.1.0). The preceding 660-check suite was not rerun.
• Both successful steps completed 0:0 and cleaned up their runtime mounts. Earlier helper API, missing jq, and unavailable-sanitizer attempts remain preserved; they were preparation failures, not top-k correctness passes.

The native memcheck command was:

compute-sanitizer --tool memcheck --error-exitcode 1 --target-processes all \
  --log-file /output/memcheck-%p.log .venv/bin/python -m pytest \
  tests/kernels/attention/test_minimax_m3.py -q \
  -k 'decode_index_topk_nan_forced_blocks_and_strides or decode_index_topk_concurrent_calls_and_replay' \
  -o cache_dir=/output/pytest-cache --basetemp=/output/memcheck-tmp \
  --junitxml=/output/memcheck-pytest.xml

Private integration with grid policy 8d807f222710e9101ba0fe176d15b31fbe8762c9 also passed on Austin: 82 checks, 0 failed/skipped, including 36 graph replays, in 343.3 s. This compared the exact grid-only source with its four grid changes applied to this fusion (combined source SHA-256 19710c827648aa64181f4a20a40965fb224e015a17d60b42c7f000d7bc7636ab); the installed standalone source and this PR were unchanged.

• 34 matched ordered-ID cases and 34 selector-reuse/counter-reset checks passed at tile/warp/stage configurations (64,2,2) and (128,4,2) across 15 page-cap boundaries, including 9 and 65 pages.
• All 244 observed launches had consistent producer counts, partial buffers, counter dimensions and merge widths. Twelve graph states covered shrinking/growing live lengths with three replays each.
• Both deliberate cross-configuration tie fixtures matched exact IDs in this subset. This does not imply universal tie ordering or default-autotune equivalence. No combined-overlay memcheck, performance or model result is claimed.
• The integration step completed 0:0 and released both runtime mounts. An independent Astra/xhigh artifact audit found no discrepancies in the launch observations or 34 SM120/PDL PTX records.

Private model-validation controls needed an LF-only JSONL parsing fix: Unicode separators inside a valid recorded prompt were incorrectly treated as record boundaries. The original shared-baseline runner failed after inference and remains recorded as failed. The corrected reader verified all 1,319 questions / 2,638 filter records against the pinned dataset without changing result/sample bytes. 18 focused CPU regressions passed, 0 failed/skipped, including Unicode separators and malformed/truncated-input rejection; 96 existing control checks passed. These are validation-harness checks, not candidate model qualification. The separate shared baseline at 8c87c333b84c85908b1d11f0044457692277c6f3 was subsequently sealed and accepted for exact matching reuse: all 1,319 questions / 2,638 filter records, 95.91% strict and 95.83% flexible accuracy. That baseline result does not validate this candidate; the individual 70fc451a5e model run remains unexecuted.

Standalone Austin timing at the same 70fc451a5e source completed with 10 measured cases: 9 stable under the predefined checks, 1 inconclusive. The complete public score-plus-selection wrapper was timed using FlashInfer CUPTI CUDA graphs with cold L2, 25 warmups, and three ABBA rounds of 31 samples per block (120 blocks / 3,720 samples, all retained). Host allocation, input generation, JIT, and the L2 flush were outside the measured device span; counter initialization/reset remained inside. All 11 pre-timing and 10 post-timing comparisons passed with exact ordered IDs; 0 failed/skipped. The separate trace confirmed three kernels becoming two without a fill launch. The step completed 0:0 and cleaned up its mounts.

Shapes are (batch, query length, indexer heads, context tokens), with BF16 inputs, head dimension 128 and top-k 16. Latencies are medians across arm-block medians:

Shape	Base (µs)	Fused (µs)	Fused latency change
(1, 1, 1, 129)	9.985	9.664	-3.21%
(4, 1, 4, 129)	8.352	7.904	inconclusive
(16, 4, 1, 129)	9.072	7.904	-12.87%
(1, 4, 1, 8192)	12.528	12.320	-1.66%
(4, 1, 4, 8192)	18.961	18.496	-2.45%
(16, 4, 4, 8192)	42.608	41.824	-1.84%
(1, 1, 4, 65536)	27.920	28.305	+1.38%
(4, 4, 1, 65536)	74.192	74.880	+0.93%
(8, 1, 4, 131072)	251.794	251.889	+0.04%
(32, 4, 4, 32768)	249.346	248.481	-0.35%

The inconclusive case retained an anomalous first baseline block (~16.7 µs versus ~8.3 µs later). It was the first CUPTI session after the launch-count profiler; profiler/session interaction is a hypothesis, not an established cause. A focused retest will move profiling after all paired timing and include the two 64K cases with consistent small slowdowns (+0.384 µs and +0.688 µs). No source change has been made from this initial timing result. Harness SHA-256: 751d8614c1ad88b0bc0016783eee1057843de4eb9663ba2f6a7524bd8eb15edc.

Full candidate MiniMax/GSM8K validation remains pending new runtime/baseline eligibility checks and a fresh model grant. As of 2026-09-11, the previous validation allocation is terminal and all historical execution grants are retired. The focused three-case retiming and individual candidate model run require fresh assigned resources. Shared-baseline and compound-stack results are not used as this PR’s individual speedup or accuracy evidence. No candidate model qualification or whole-recipe speedup is claimed; this PR remains a draft.
Upstream CI note: both pre-commit pre-run checks stopped at the contributor/label eligibility gate, so upstream pre-commit was skipped; this was not a source-test failure (first run, second run). DCO and documentation checks passed. Full upstream CI and human review remain unclaimed.

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