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Thanks for the look. #55059 is discussed in the description, this PR is a different implementation with a wider
Either way works for me, keep this PR, or, if #55059 is the preferred, |
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let's land #55059 first |
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This pull request has merge conflicts that must be resolved before it can be |
… for the Triton iHC path Follow-up to vllm-project#55059. The Triton iHC pre/post kernels are now registered as custom ops with fake impls (torch.compile / CUDA-graph safe) and gain a head variant (pre without the post gates, HAS_POST=False, same two kernels), so HYV4HCHeadLayer no longer runs the 15-launch torch path. Adds a startup warmup, parity tests for all three ops against the eager layers, opcheck, a model-level test through the engine, and torch.compile + head columns in the benchmark. Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com> Signed-off-by: Takymu <takymu@duck.com>
Follow-up to vllm-project#55059 (kept as the decode path). From 128 tokens per step pre/head switch to a two-launch stats + apply pair: the [T, 4d] x [4d, 8] projection runs on tensor cores with the fp32 weight as a bf16 hi+lo pair and the hidden dim split across programs; 1.2-1.5x over the vllm-project#55059 kernels at 256-4096 tokens (CUPTI, cold L2) on RTX 5090 and RTX PRO 6000, crossover between 96 and 128 tokens on both. post uses one program per (token, channel, hidden tile) with the tile index fastest, so consecutive programs stream consecutive memory, plus PDL: 1.3-1.9x over the vllm-project#55059 post at <= 32 tokens, 1.2x at 64, equal above, and within 0.93-1.05x of torch.compile everywhere. The warmup enumerates the compile keys of the new path (warmup_token_sizes) so nothing JITs on the first request. Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com> Signed-off-by: Takymu <takymu@duck.com>
flashinfer's bench_gpu_time_with_cupti only rotates the buffers it can see in input_args; with the inputs bound in a partial the cold-L2 rotation was silently disabled, and without cupti-python it silently fell back to CUDA events while the header still said "cupti". Pass the inputs explicitly and fail loudly when cupti-python is missing (or use --method cudagraph). Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com> Signed-off-by: Takymu <takymu@duck.com>
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Takymu
changed the title
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Rebased on top of #55059 and reworked as a follow-up to it rather than a replacement: the #55059 kernels stay as the decode path; this PR adds the Head-to-head numbers are in the description. @jeejeelee PTAL when you have a moment. |
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This pull request has merge conflicts that must be resolved before it can be |
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[Kernel][HY-V4] iHC: head op, custom-op registration, tensor-core path for large batches, warmup and tests
Purpose
Follow-up to #55059, which added Triton kernels for the HY V4 iHC
preandpostops(the 4-channel residual mixing that runs twice per decoder layer, 156 times per token).
This PR keeps those kernels as the decode path and completes the iHC Triton path:
headis covered. The final channel merge before the output norm was still on the15-launch torch path; it is
prewithout the post gates, so the [Kernel][HY V4] Add Triton iHC pre/post fallback #55059 kernels gain aHAS_POSTconstexpr and serve it (triton_ihc_head).pre/post/headare registered astorch.ops.vllm.hy_v4_ihc_*(direct_register_custom_op), so the launches stay opaque totorch.compile and are safe inside piecewise CUDA graphs; checked with
torch.library.opcheck.concurrent requests in decode)
pre/headswitch to a two-launch stats + applypair: the
[T, 4d] @ [4d, 8]projection runs on tensor cores with the fp32 weight splitinto a bf16 hi+lo pair (fp32-level accuracy), the hidden dim split across programs.
Against the [Kernel][HY V4] Add Triton iHC pre/post fallback #55059 kernels (CUPTI, cold L2): 1.2-1.5x on
preat 256-4096 tokens onRTX 5090 and RTX PRO 6000; the crossover is between 96 and 128 tokens on both, so below
128 the [Kernel][HY V4] Add Triton iHC pre/post fallback #55059 two-stage kernels stay in use unchanged.
postre-gridded. One program per (token, channel, hidden tile) with the tile indexfastest, so consecutive programs stream consecutive memory of the
[T, 4, D]residual andoutput, plus PDL. The [Kernel][HY V4] Add Triton iHC pre/post fallback #55059
post(one program per (token, tile), all channels inside)is 0.6-0.8x of
torch.compileat 64-128 tokens and 1.5-1.9x slower than this one at1-8 tokens; the new one is within 0.93-1.05x of
torch.compileat every size measured(bandwidth-bound: 1.5 TB/s on both GPUs at large T).
warmup_token_sizes()enumerates the Triton compile keys reachable forT <= max_num_batched_tokens(the large-batch path's keys depend on the batch size) andhy_v4_ihc_warmuplaunches each once, hooked intokernel_warmupnext to the DeepSeek-V4mHC warmup, so nothing JITs on the first request.
boundary), opcheck, warmup coverage, and a model-level test through the engine.
Tbelow is the number of tokens in the batch (all requests of a step together). The modelis not
@support_torch_compile-wrapped, so vLLM runs it withCompilationMode.NONEand the"eager" numbers are what the torch path costs in production.
Benchmark note: the #55059 script passed the inputs to flashinfer's timer inside a
partial,which silently disables its cold-L2 rotation, and fell back to CUDA events when
cupti-pythonis missing while still printing "cupti". The script now passesinput_argsand fails loudly without CUPTI; all numbers below are with CUPTI and a cold L2, which is
20-40% slower than warm-L2 numbers for these bandwidth-bound ops.
Relation to other PRs: #55059 (merged) is the base this PR builds on; its kernels are kept
and extended, not replaced. #54432 / #54594 are the AMD side (
vllm/models/hy_v4/amd/) anddo not touch this path. The threshold and the head-to-head numbers were measured on RTX
5090 and RTX PRO 6000 Blackwell (no H100 at hand at the moment);
_LARGE_T_MINis aone-line constant if the crossover differs on Hopper.
Test Plan
pytest tests/models/hy_v4/test_ihc_ops.py— parity ofpre/head/postagainst theeager layers (Triton dispatch disabled) over T in {1, 2, 7, 16, 127, 128, 129, 300, 1024},
hidden in {512, 4096, 6144}, bf16/fp16; channel-strided input; gate math with zero weights;
torch.library.opcheckfor the three ops;warmup_token_sizescovers every compile key(checked against the Triton JIT cache after running T = 1..2048).
pytest tests/models/hy_v4/test_ihc_e2e.py— one-layer dummy-weightHy4-preview(real hidden size,
hc_mult, sparse MLA) through the engine with CUDA graphs, greedylogprobs of the Triton path vs the eager path (
check_logprobs_close), fused op assertedto be dispatched. Needs a GPU with a sparse-MLA backend.
tests/models/test_initialization.py -k HYV4ForCausalLM.benchmarks/kernels/benchmark_hy_v4_ihc.py(the [Kernel][HY V4] Add Triton iHC pre/post fallback #55059 script, extended withheadand atorch.compilecolumn, inputs passed viainput_args); CUPTI, CUDA graph replay, cold L2.pre-commit run --files ....GSM8K on the real checkpoint (~800B parameters) needs an 8-GPU node I do not have; the
model-level test plus the op-level parity tests are what I could run.
Test Result
tests/models/hy_v4/test_ihc_ops.py: 168 passed;tests/models/hy_v4/test_ihc_e2e.py:passed (eager vs Triton logprobs match through the engine, CUDA graphs on);
test_initialization -k HYV4ForCausalLM: passed;pre-commitclean. Run on RTX 5090 and onRTX PRO 6000 Blackwell, both on top of 7fa2c63 (main with #55059).
Against the #55059 kernels
Same inputs, bf16, hidden 6144 (the model's size), median us per call, CUPTI, CUDA graph
replay, cold L2;
x= #55059 time / this PR time. Below 128 tokenspreruns the unchanged#55059 kernel on both sides (differences there are timer noise).
headhas no #55059counterpart (it ran on the torch path: 24 us at 1 token).
RTX 5090:
RTX PRO 6000 Blackwell (188 SMs, 96 GB):
Same, hidden 4096
RTX 5090:
RTX PRO 6000 Blackwell:
Reading: the tensor-core path takes over at 128 tokens and reaches 1.2-1.5x at 256-4096
tokens, i.e. prefill and high-concurrency decode; at 1-64 tokens
preis unchanged.postis 1.3-1.9x at <= 32 tokens, 1.2x at 64 and within noise of the #55059 kernel from 256 on
(0.96-1.22x; both bandwidth-bound there). The crossover sweep (32-256 tokens) is below;
_LARGE_T_MIN = 128is above the crossover on both GPUs.Crossover sweep (CUPTI, cold L2)
RTX 5090:
hidden 4096 (us):
hidden 6144 (us):
RTX PRO 6000:
hidden 4096 (us):
hidden 6144 (us):
Eager vs torch.compile vs Triton (RTX 5090, hidden 6144, bf16, CUPTI, CUDA graph, cold L2)
eager= the torch path the model runs today;compile=torch.compileof that path;x= time / Triton time. The >20xx compilecells at 2-16 tokens on the 5090 come fromcuBLAS picking a poor split-K algorithm for the tiny-M fp32 projection in the compiled
baseline (not seen on the PRO 6000 or on H100/A100).
RTX 5090, hidden 4096
RTX PRO 6000 Blackwell, hidden 6144
H100 SXM / A100 PCIe: tensor-core pre/head path, measured on an earlier revision
The tensor-core
pre/headpath is unchanged from an earlier revision of this branch thatwas measured on H100 (driver 550, torch cu129) and A100 40GB (driver 595, cu130), warm L2
(the timer issue above), so these rows are indicative only;
postrows are omitted (thekernel changed since). Rows for the #55059 kernels are omitted too.
H100 SXM 80GB:
A100 PCIe 40GB:
AI assistance
Written with Claude (Anthropic) as an assistant; I reviewed every line, ran the tests and
benchmarks listed above and am responsible for the change. Commits carry a
Co-authored-by:trailer.