[Qwen4Exp][ROCm] Support FP8 PLE n-gram checkpoints on the AMD path - #55040
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FP8 checkpoints store the PLE n-gram table shards as F8_E4M3 with one global per-tensor scale (ngram_embedding.weight_scale). The AMD path had no handling for either, so FP8 PLE tables could not load on ROCm. Fold the scale in at load time and keep the in-memory table in bf16 (same convention as transformers' FP8Embedding). Two AutoWeightsLoader subtleties are handled explicitly: weights may arrive as a single-pass generator, and the PLE weights may be split across several load_weights calls (one per consecutive checkpoint-file group) with the scale in only one of them. Co-authored-by: DeepSeek Harness Agent <noreply@deepseek.ai> Signed-off-by: jebchowDCGPU <312339234+jebchowDCGPU@users.noreply.github.com>
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Sharing an end-to-end MI300X (gfx942) data point for this configuration, since the PR's validation is on MI350X and MI300X TPS/VRAM numbers came up as an open question. Caveat first: these numbers are not from this branch verbatim. They come from a source build ( Host / serve config:
Memory [measured]: VRAM 170.1/191.7 GiB at 0.90 utilization with the PLE table fully off-GPU; KV cache capacity ~1.27M tokens; host RAM 220 GB with the 47.7 GiB table resident in page cache (zero major faults sampled during decode). Throughput [measured] (streaming, temperature 0, usage-based token counts):
MTP N=3 on general text: server-wide acceptance 0.667, mean accepted length 2.7–3.0 tokens/step, per-position 0.79/0.53/0.38. GPU busy 81–92% during single-stream decode, so the step cost is the model forward, not host-table gathers. Tool calling round-trips correctly with Two operational notes: FULL cudagraphs are rejected under mmap by design (the gather must run outside capture), so PIECEWISE is the ceiling in this configuration; and per-stream throughput settles around 22 tok/s under 4–8-way concurrency while aggregate scales near-linearly, so the box is not saturated at Happy to share bench scripts or full logs if useful. |
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Purpose
FP8 checkpoints of Qwen3.8-Flash-Next store the PLE n-gram table
(320,001,536 rows × 160 dims, 128 shards) as
F8_E4M3with one globalper-tensor scale (
ngram_embedding.weight_scale). The NVIDIA path handlesthis at runtime (
embeddings × weight_scale, #54722); the AMD/ROCm path hadno handling for either, so FP8 PLE tables could not load on ROCm.
This adds load-time dequantization on the AMD path: fold the scale into the
shards and keep the in-memory table in bf16 (same convention as
transformers'
FP8Embedding).Two
AutoWeightsLoadersubtleties are handled explicitly:weightsmay be a single-pass generator. The scale pre-scanmaterializes the iterable; the main loop must iterate the materialized
list. Re-iterating the parameter silently loads nothing — and the strict
unloaded-weights check is disabled for quantized models, so the failure
is completely silent (the table stays at
torch.emptyinit).load_weightscalls._groupby_prefixonly groups consecutive same-prefix entries; e.g.model-00037ofQwen/Qwen3.8-Flash-Next-FP8interleaveskey_proj/norm_*weights betweenple_embeddingweights, producingtwo calls. The scale arrives in only one of them, so it is cached on the
module — otherwise the later shards load as raw FP8 (~2000× too large),
which garbles generation at ~1/16 lookup frequency (the table tail is
the last trigram hash head).
Not a duplicate: #54722 (merged) and #54882 (open) cover the NVIDIA path
only; #53899's AMD path has no FP8 handling; #54129/#54070 are disk-backed
table features. No existing issue tracks the AMD-path gap; found while
serving the FP8 checkpoint on MI350X.
Test Plan
New unit tests in
tests/models/qwen4_exp/test_ple.py, mirroring theexisting NVIDIA-path tests:
test_amd_ngram_embedding_loads_fp8_shards_with_folded_scale—single-pass generator input (the
AutoWeightsLoaderproduction path),scale folded into bf16
test_amd_ngram_embedding_fp8_scale_cached_across_split_calls— splitload_weightscalls with the scale only in the first (thecheckpoint-file-group split)
Test Result
Both new tests pass against this change.
End-to-end on MI350X (gfx950, ROCm 7.2.3,
Qwen/Qwen3.8-Flash-Next-FP8,MTP speculative decoding + prefix caching + CUDA graphs, TP=1):
Before this change the FP8 PLE table was silently dropped (PLE effectively
disabled); with only the generator fix, 126/128 shards loaded correctly
and the last two loaded as raw FP8, garbling ~1/16 of lookups.
GSM8K (full 1,319 problems, chat API, greedy, thinking off):
95.98% (1266/1319)
MMLU-Pro (thinking mode, 140-question stratified subset, greedy):
78.57% (official card: 73.23; direct/CoT subsets: 69.80% / 66.53%)
AI assistance was used to develop and validate this change (root-cause
analysis, fix, tests, and evaluation). The submitter has reviewed every
changed line and takes full responsibility for the contribution.
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supported_models.mdandexamplesfor a new model.