[Perf][Attention][DSA] Shard prefill indexer rows across TP ranks

[RichApple123]

Summary

Fixes #53691.

The CUDA DSA prefill indexer currently recomputes the same logits and Top-K results on every tensor-parallel rank. This PR assigns each independent prefill query row to one TP rank, scores that row against its complete key interval, and reconstructs the original Top-K layout with one all_gatherv per indexer layer.

Only finished int32 Top-K indices are exchanged. This is not an approximation or a merge of partial candidates: each row has exactly one writer, so there is no cross-rank score/tie merge and no index-only MAX reduction.

Design and invariants

The partition is contiguous and balances the exact number of scored keys using replicated CPU scheduler metadata:

cost(request, j) = (seq_len - query_len + 1 + j) // compress_ratio

A cumulative sum plus searchsorted produces a positive, exhaustive partition for any TP size without a device synchronization.

Four boundaries keep the change local and safe:

• KV state stays replicated. KV gathering runs before the row intersection on every rank, preserving the existing skip_kv_gather workspace-reuse contract across chunks.
• Decode stays replicated. Mixed-batch decode rows [0, num_decode_tokens) remain on the stock path. Ownership and all_gatherv cover only the following prefill slice.
• The collective decision is rank-consistent. row_shard_sizes is derived from replicated metadata and static configuration; a rank-local runtime predicate cannot make only some ranks enter the collective.
• Unsupported/small workloads fall back. The existing replicated implementation remains unchanged and is selected conservatively.

The sharded path requires CUDA, TP > 1, sparse-MQA prefill, at least 1,024 scheduled prefill rows per rank, PyNCCL, no DCP/PCP, no NCCL symmetric-memory all-gather, no batch-invariant mode, and a mixed-batch CUDA Graph mode other than FULL.

Performance

Unless noted otherwise: 4 × NVIDIA H20, DeepSeek-V4-Flash, TP=4, clean stock/patched processes.

Indexer critical path

At a 4,098-row fresh prefill, measured across 21 DSA indexer layers with CUDA-event medians, the distributed critical path is the slowest rank rather than the rank average:

Implementation	Critical indexer time	Delta	Speedup
Replicated	0.229 ms	—	1.00×
Balanced rows + all_gatherv	0.173 ms	-24.5%	1.32×

The measured row split was [2049, 849, 651, 549]. On the patched critical rank, scoring took 0.069 ms and exchange/wait took 0.103 ms; communication is included rather than hidden.

Why the activation floor is 1,024 rows/rank

A dedicated sweep used the production score/Top-K kernels and production PyNCCL all_gatherv (maximum per-rank median, 31 samples after 8 warmups):

Rows/rank	Replicated	Sharded + exchange	Delta	Speedup
512	0.0966 ms	0.1666 ms	+72.5%	0.58×
1,024	0.2504 ms	0.1860 ms	-25.7%	1.35×
2,048	0.7414 ms	0.3531 ms	-52.4%	2.10×

512 rows/rank does not amortize the collective; 1,024 is the first measured profitable point and the benefit grows with work. The value is an internal conservative performance gate, not a correctness condition or public tuning knob. The exact crossover is model, kernel, collective, and hardware specific.

End-to-end serving

Three repetitions per arm, prefix caching disabled:

Workload	Stock tok/s	Patched tok/s	Throughput	TTFT
C1, 4K	8,622.8	8,643.7	+0.24%	-0.24%
C2, ragged 8K total	8,722.8	8,745.9	+0.26%	-0.84%
C4, ragged 15.6K total	9,048.6	9,090.3	+0.46%	-0.34%
C2, ragged 16.3K total	9,117.7	9,181.2	+0.70%	-2.76%
C1, 16K	8,981.7	9,158.5	+1.97%	-1.91%
C1, 32K	8,803.5	9,120.7	+3.60%	-3.48%

The long-context retrieval runs show the intended scaling regime:

Prompt tokens, C4	Stock median latency	Patched median latency	Delta
65,377	36.972 s	34.695 s	-6.2%
130,402	78.822 s	70.265 s	-10.9%

KV gathering remains replicated and collective wait is fixed overhead, so the gain increases as the scored key history grows.

Correctness and compatibility

Gate	Stock	Patched
Needle retrieval, 65,377 tokens, 16 positions	16/16	16/16
Needle retrieval, 130,402 tokens, 16 positions	16/16	16/16
GSM8K, 1,319 questions, 5-shot	93.9348%	94.3897%
Native DSpark, accepted / draft tokens	865 / 2,184 (39.61%)	850 / 2,156 (39.42%)

The DSpark comparison used TP=4, 7 draft tokens, three repetitions per arm, and four concurrent ragged/chunked-prefill requests per repetition. Mean acceptance length was 3.772 stock vs 3.760 patched. All 24 requests returned HTTP 200 with non-empty output and no CUDA/NCCL errors. The -0.18 percentage-point aggregate acceptance difference is smaller than run-to-run variation; this is compatibility/non-regression evidence, not a statistically powered quality claim. N-gram speculative decoding also completed with the row-sharding gate active.

PIECEWISE CUDA Graph captured 51/51 graphs and completed sharded prefill plus decode without a capture error. Explicit FULL captured and generated successfully while conservatively retaining the replicated prefill path.

For continuous random logits, three H20 actual-kernel replays found zero full-vs-sharded selected-set differences. Synthetic exact-tie differences were confined to zero-margin rows with identical selected-score multisets; unchanged stock and sharded launches both exhibit the existing kernel's tie nondeterminism. A deterministic kernel tie-break is orthogonal to this PR.

Tests

• pytest -q tests/v1/attention/test_indexer_tp_row_shard.py tests/v1/attention/test_indexer_dcp_localize.py tests/v1/attention/test_indexer_deepseek_v4_slot_mapping.py tests/v1/attention/test_indexer_native_next_n.py tests/model_executor/layers/test_mla_short_prefill_indexer.py — 84 passed, 22 skipped
• Post-review row-sharding suite — 56 passed, including exact sparse-MQA routing boundaries, mixed decode/prefill with padded tails, repeated query ranges, alternating KV-gather reuse, and all enablement fallbacks
• Focused pre-commit — all hooks passed
• Service coverage — TP=4 concurrency 1/2/4, ragged/mixed requests, chunked prefill, 4K–130K contexts; TP=2 C1/C2 smoke tests
• Pure/simulated TP=2/3/4/8 partition and collective coverage

TP=8 hardware was unavailable. TP=8 partition/collective behavior is unit-tested, but its performance scaling remains unmeasured.

Related work / non-duplication

• [ROCm][Perf] TP-shard Lightning indexer prefill #46103 implements the same disjoint-row principle for ROCm/gfx950; this PR covers NVIDIA/CUDA and adds scored-key balancing plus conservative KV-workspace handling.
• [Perf][GLM-5.3-Flash] Shard long-context indexer prefill rows across TP #54951 was opened after this PR and extends the pattern to GLM-5.3's k-pool indexer. Its 16K rows/rank floor is a separate GLM/H200 policy; this PR's 1K DSA/H20 floor is backed by the crossover measurement above.
• [Perf][Kernel] Fused DSA indexer Top-k kernel (LiteTopk) #48726 and [RFC]: SM90 Exact Fused DSA Prefill Indexer #53563 optimize indexer kernels/materialization and are orthogonal to eliminating TP-replicated work.
• [DCP][Kernel] Consume owner-sharded Top-K candidates through symmetric memory #50366 merges owner-sharded candidates for DCP. This PR owns complete rows, so it needs layout reconstruction rather than a (score, global_id) candidate merge.

AI assistance

Parts of this change were drafted with AI assistance. The author reviewed the final diff, tests, and validation evidence before submission.

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[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @RichApple123.

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[kalenforn]

Thanks for working on this — I am the author of #53691. We independently built the index-MAX-union variant of the same row-sharding idea (each rank scores a disjoint row slice and merges partial top-k buffers with an
elementwise max) and hit two correctness walls, both of which this PR's row-owned design avoids by
construction — with one ownership question we'd ask you to spell out below (§3). Numbers from our
side, all measured in serving on TP4/TP8 H100 with a ds-v4-flash-class model:

1. Exact-tie launch nondeterminism in the top-k kernel itself (affects stock too, independent of
sharding):

• the top-k boundary occasionally hits an exact fp32 tie; the kernel's final insertion pass
  resolves ties by shared-memory registration order (thread-scheduling-dependent, not
  input-dependent). Every dumped flip row has boundary margin exactly 0.0 (44/44); re-launching the
  same input 100× flips the selected set on 12.1% of launches (stock kernel);
• with a deterministic tie-break (fixed index preference on ties) patched in, launch flips drop to
  0/4400 and all patched-vs-stock differences are confined to margin-0 rows.

Implication: since flip-class divergence is selection within a score-equivalent set, a row-owned
top-k is equivalent to stock in information terms. Two consequences worth stating in the PR:
quality gates should use multiple seeds/runs (single-run retrieval gates can mask tie-amplified
differences — we measured 4/16 vs 16/16 needle retrieval across draws of the same config); and if
upstream ever wants bit-reproducible serving, the kernel-level deterministic tie-break is the
lever — happy to share the patch and replay harness.

2. Decode rows must never enter an elementwise merge union. Our variant's merge
(all_reduce(MAX) over the shared top-k buffer) is correct for prefill rows — each row is written
by exactly one rank — but decode rows are written by every rank, so the elementwise MAX becomes
a max over claim-order permutations of one set, which is not a permutation: it fabricates
duplicates and loses members. Measured directly by dumping cross-rank decode buffers in serving:
on one nd=1 call, the hypothetical MAX fabricates 161 duplicate slots and loses 161 members. We
confirmed causally with two independent mechanisms at a 16-prompt long-context retrieval gate
(ISL 65k, greedy): (a) snapshot/restore of decode rows around the union: 16/16 (vs 4/16 without);
(b) our production fix — restrict the collective to rows [nd, n) so decode rows stay rank-local:
16/16, engagement verified over 8k+ serving-phase applications. If any sharding variant keeps a
merge step, the decode/prefill row boundary has to be excluded from the collective.

3. A question for this PR's design: who owns the decode rows in a mixed batch? The mechanism
above is not specific to our merge — it is a write-ownership question every cross-rank indexer
design has to answer. In our engine the decode selection is replicated: all TP ranks compute the
full decode top-k (they must agree on the selected KV pages), and prefill chunks and decode steps
share one call path in mixed batches. Row-owned gatherv sidesteps the merge class, but if the
per-spec banding ever assigns a decode row's ownership per-rank while every rank still computes it
(or vice versa), the same one-writer/many-writer mismatch reappears one level up. Worth stating
explicitly in the PR how bands are constructed for decode rows in mixed prefill+decode batches.

4. We measured this PR's collective head-to-head against ours: no performance argument against
it, and its output is bit-identical. We ran a pre-registered A/B in serving (TP4 H100, real
agentic replay workload, 10 traces × 7 runs per arm per concurrency, single variable = the merge
collective — identical shard stack otherwise; your per-spec all_gatherv vs our
all_reduce(MAX) over the owned prefill slice):

	per-spec all_gatherv (this PR)	all_reduce(MAX) slice (ours)
Correctness — live bitwise self-check vs the MAX-union, 30 applies per arm under real traffic	60/60 bit-identical, 0 mismatches	reference
Merge cost per full-chunk (8192-row) call, conc 1 — median ms [p25–p75] (n)	0.153 [0.142–0.163] (6,164)	0.175 [0.161–0.183] (5,689)
Merge cost per full-chunk call, conc 4 — median ms [p25–p75] (n)	0.156 [0.143–0.176] (10,878)	0.167 [0.155–0.178] (10,857)
Timed merge calls per arm (engagement; conc 1 / conc 4)	22,010 / 25,570	20,893 / 25,599
End-to-end TTFT ratio (gatherv ÷ ours)	0.998 (c1) / 1.021 (c4) — inside cross-boot noise	1.0

Read: both collectives cost ~0.15–0.17 ms per full-chunk merge call; gatherv's median is 6–12%
lower but the intervals overlap, so under our pre-registered three-branch rule the difference is
not resolvable; end-to-end TTFT moves <0.25% and stays inside cross-boot noise. So from our
measurements: no reason to prefer keeping a merge layer on performance grounds — the
structural-immunity argument stands on its own. For context, our duplicate-work finding in
#53691 (the indexer scoring running 8×-replicated under TP) is the workload side of the same
story; this PR is the fix we would want upstream to take.

No non-tie divergence observed between sharded and stock scoring (fp8 logits GEMM bit-identical,
98,304/98,304 offline; byte-level 0/250,520 dumped rows differ).

---

[coderabbitai]

Walkthrough

The DSA indexer now shards independent prefill query rows across TP ranks. It balances rows by compressed-key cost, gathers rank-local top-k results, preserves KV metadata behavior, and adds coverage for correctness and unsupported configurations.

Changes

TP Prefill Row Sharding

Layer / File(s)	Summary
Sharding policy and metadata contract vllm/v1/attention/backends/mla/indexer.py	Adds balanced row partitioning, configuration gating, and optional row_shard_sizes metadata.
Prefill metadata construction vllm/v1/attention/backends/mla/indexer.py	Computes row shards for eligible MQA prefill workloads and stores the distribution in prefill metadata.
Rank-local scoring and result reassembly vllm/model_executor/layers/sparse_attn_indexer.py	Scores rank-local row ranges, preserves narrowed metadata and weights, and reconstructs the complete top-k buffer through TP all-gather.
Correctness and support validation tests/v1/attention/test_indexer_tp_row_shard.py	Validates row-independent results, chunk boundaries, cost balancing, fallback behavior, and configuration gates.

Estimated code review effort: 4 (Complex) | ~45 minutes

Merge Risk: 🟡 Moderate · up to cae5d

TP prefill row sharding can fail on padded batches during result reassembly, so the destination count should be corrected before merge. The configuration-gate tests should also isolate all environment flags to remain reliable.

Sequence Diagram(s)

sequenceDiagram
  participant PrefillMetadataBuilder
  participant TPIndexerRank
  participant IndexerKernel
  participant TPGroup
  PrefillMetadataBuilder->>TPIndexerRank: provide row_shard_sizes
  TPIndexerRank->>IndexerKernel: score assigned prefill rows
  IndexerKernel-->>TPIndexerRank: return local top-k results
  TPIndexerRank->>TPGroup: exchange local top-k buffers
  TPGroup-->>TPIndexerRank: return complete top-k layout

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Suggested reviewers: zjy0516

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 56.00% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 25 functions across 3 files.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Linked Issues check	✅ Passed	The changes address issue #53691 by removing redundant CUDA DSA prefill computation, preserving row-wise Top-K correctness through disjoint ownership and all-gather reassembly, retaining KV-gather beh…
Out of Scope Changes check	✅ Passed	The modified implementation and added tests remain within the linked issue scope. They cover TP prefill row sharding, balancing, gating, collective behavior, correctness, and performance without unrel…
Title check	✅ Passed	The title clearly and concisely describes the main change: sharding the DSA prefill indexer rows across tensor-parallel ranks.
Description check	✅ Passed	The description directly explains the row-sharding design, compatibility constraints, performance results, correctness validation, and test coverage for the changeset.

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Actionable comments posted: 2

🤖 Prompt for all review comments with AI agents

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Inline comments:
In `@tests/v1/attention/test_indexer_tp_row_shard.py`:
- Around line 419-421: Update the test setup around
tp_prefill_row_sharding_supported to apply env entries with monkeypatch.setenv
instead of materializing indexer.envs attributes, and explicitly define
VLLM_USE_NCCL_SYMM_MEM, VLLM_BATCH_INVARIANT, and the remaining relevant flag in
every test case, including env={} cases.

In `@vllm/model_executor/layers/sparse_attn_indexer.py`:
- Around line 559-561: Update the prefill destination slice around
topk_indices_buffer and the all_gatherv call to use the unpadded prefill token
count derived from shard_sizes, matching the row count returned by all_gatherv.
Replace the padded num_prefill_tokens-based endpoint while preserving the decode
offset and existing top-k assignment.

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[RichApple123]

Thanks for the detailed analysis and the head-to-head measurements. They were especially helpful in clarifying the decode-row ownership requirement and the distinction between score equivalence and bitwise reproducibility.

I have updated the PR to state the mixed-batch ownership boundary explicitly:

• decode rows [0, num_decode_tokens) remain replicated and are computed independently on every TP rank, exactly as in the existing path;
• row ownership applies only to the subsequent prefill window;
• shard_start includes the decode offset, while all_gatherv reads from and writes to only the prefill slice, so decode rows never enter the collective;
• the integration test places sentinel decode rows before the prefill window and verifies that the exchange leaves them unchanged.

I also replayed the actual top_k_per_row_prefill CUDA kernel on H20 with 4,098 rows × 16,384 keys, Top-K 2,048, the measured [2049, 849, 651, 549] partition, and three independent seeds.

For continuous random logits, the full-row and row-sharded launches produced identical selected sets for every row across all three seeds.

In a deliberately tie-amplified stress test, exact ties caused 4,092–4,097 rows per seed to select different index sets. However, every differing row had a zero Top-K boundary margin, and the selected score multisets were identical. Re-launching each unchanged tied input 50 times also changed the selected set for both the full-row and row-sharded launch shapes. This confirms that the bitwise variation originates in the existing kernel's tie handling rather than in row sharding. The dense-tie case is intended as a mechanism-level stress test, not as an estimate of the production flip rate.

Your all_gatherv versus MAX-union A/B is also reassuring. Although the per-call medians slightly favor all_gatherv, the end-to-end difference remains within cross-boot noise, so there is no performance argument against choosing the structurally safer row-owned gather design.

This should address the mixed-batch ownership question in §3. Please let me know if you see any remaining ownership mismatch or boundary case in the updated design.

[RichApple123]

Hi, this PR has been rebased onto current main and is now mergeable. I have personally reviewed the final diff and validation results. The focused tests, pre-commit checks, and DCO all pass, and the mixed-batch ownership concern raised in the discussion has been addressed.
Could a maintainer please review the PR and, if appropriate, add the ready label so that upstream CI can run?

[JaredforReal]

same question as #54951, have u ever tried this feature with SpecDecode Enabled?
a little bit concern right here

Thanks for this great feature @RichApple123

[JaredforReal]

MIN_TP_SHARD_ROWS_PER_RANK=1K
can u give us more detail that why u choose 1k right here? cuz #54951 uses a much bigger number, and I don't really know if we hardcoded this number is a good idea?

[JaredforReal]

we have unit tests for tp_prefill_row_sharding_supported, we may need similar unit tests for prefill_uses_mqa right here

[RichApple123]

Thanks for the careful review. I went through all three points and updated the PR description. The current head (60f6f0b) already contains the corresponding gating/test changes.

1. Why 1,024 rows/rank, and why keep it as a constant?

   I measured the crossover on 4×H20/TP=4 using the production DSA score/Top-K kernels and the production PyNCCL all_gatherv, taking the maximum per-rank median over 31 samples after 8 warmups:

   Rows/rank	Replicated	Sharded + exchange	Delta	Speedup
   512	0.0966 ms	0.1666 ms	+72.5%	0.58×
   1,024	0.2504 ms	0.1860 ms	-25.7%	1.35×
   2,048	0.7414 ms	0.3531 ms	-52.4%	2.10×

   512 rows/rank does not amortize the collective; 1,024 is the first measured profitable point and the benefit grows with work. This constant is only an internal performance gate: batches below it keep the stock replicated path, so it cannot affect correctness. I kept it non-public to avoid exposing an unvalidated tuning knob. The 16K value in [Perf][GLM-5.3-Flash] Shard long-context indexer prefill rows across TP #54951 is a separate conservative policy measured for GLM-5.3/H200/k-pool; I do not think copying it directly across model/kernel/hardware combinations would be better than using the measured DSA/H20 crossover. I am happy to unify the policy later if maintainers prefer a shared architecture-specific mechanism.

2. prefill_uses_mqa coverage

   Agreed. I extracted _prefill_uses_mqa() and added a parameterized boundary test covering max_seq_len 2047/2048/2049 against index_topk=2048, plus sparse_mla_force_mqa=True on both sides of the boundary. This verifies that row sharding is enabled only when sparse MQA actually consumes the Top-K output. The post-review row-sharding suite is 56/56 passing; the broader focused suite is 84 passed, 22 skipped.

3. SpecDecode compatibility

   The design keeps speculative/decode rows on the replicated path: mixed-batch decode rows [0, num_decode_tokens) never enter row ownership or all_gatherv; only the following prefill slice is sharded. I additionally ran the model-native DeepSeek-V4 DSpark path with the patched row-sharding gate active.

   This was a clean stock-vs-patched TP=4 A/B, with 7 draft tokens, 3 repetitions per arm, and four concurrent ragged/chunked-prefill requests per repetition (4.6K/5.2K/6.1K/7.3K prompt tokens, 96 output tokens):

   Arm	Requests	Accepted / draft tokens	Draft acceptance	Mean acceptance length
   Stock	12/12	865 / 2,184	39.61%	3.772
   Patched	12/12	850 / 2,156	39.42%	3.760

   All 24 requests returned HTTP 200 with non-empty output, every run accepted draft tokens, and neither arm logged a CUDA or NCCL error. The patched aggregate differs by -0.18 percentage points in draft acceptance and -0.34% in mean acceptance length, both smaller than the observed run-to-run variation. I therefore do not observe an acceptance-rate regression from row sharding; this is compatibility/non-regression evidence rather than a statistically powered quality claim. N-gram SpecDecode also completed with sharding active.

Thanks again for raising these points—they improved both the gating evidence and the compatibility coverage.

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @RichApple123.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork