[Kernel][Perf] Fuse clamped MoE activation and UE8M0 FP8 block quantization

[zigzagcai]

Purpose

Fuse the clamped MoE activation path into FP8 block-128 activation quantization:

1. finite SwiGLU clamping;
2. BF16 SiLU and gated multiplication;
3. dynamic E4M3 block quantization, including Hopper DeepGEMM UE8M0 scales; and
4. optional filtering of invalid or non-local expert rows.

The CUDA implementation extends the existing stable-ABI silu_and_mul_per_block_quant op and has two execution strategies:

• a lightweight one-block-per-quant-group kernel for launch-bound TP decode shapes without an expert_map;
• an occupancy-driven persistent kernel when EP filtering is present or the output has at least 1M elements.

The persistent variant uses vectorized BF16 loads/FP8 stores and half-warp reductions. Both clamped variants preserve the BF16 activation materialization point and are bit-exact with the original two-kernel UE8M0 path.

The Triton experts dispatch remains narrow: CUDA, gated SiLU with a finite clamp, int32 routing IDs, FP8 W8A8 block shape [128, 128], and no LoRA activation consumer. Large unfiltered prefills fall back to the existing kernels at the measured crossover. The existing unclamped E8M0 path remains excluded because its activation semantics are not bit-exact. VLLM_USE_DSV4_FUSED_ACT_QUANT=0 is the matched A/B fallback.

Trace evidence

PyTorch profiler trace of zai-org/GLM-5.3-Flash on 4x H200, TP4, MTP=5, BF16 KV cache, CUDA graphs:

Rank-0 stable window	Calls	Total	Average
Baseline clamp	658	2042.672 us	3.104 us
Baseline per-token-group quant (all paths)	1316	3297.808 us	2.506 us
Fused target kernel	658	1389.724 us	2.112 us
Remaining non-target quant	658	1762.810 us	2.679 us

For each target MoE layer, the relevant baseline route is one clamp plus one of the two quant launches: approximately 5.65 us to 2.11 us, or 2.68x, while removing one launch. With 45 target MoE layers this saves about 159 us per target forward. The other quant launch belongs to a separate path and is intentionally unchanged.

The same trace also showed that shared-expert computation already runs on an auxiliary stream, so this PR targets the measured launch-bound activation/quantization path rather than duplicating existing computation overlap.

Kernel microbenchmarks

H200 (SM90), CUDA 13.2, PyTorch 2.13. Command for the GLM path:

CUDA_VISIBLE_DEVICES=0 python \
  benchmarks/kernels/benchmark_dsv4_fused_act_quant.py \
  --tokens 1 4 16 64 128 256 \
  --topk 8 --hidden-size 512 --num-experts 288 \
  --no-expert-filter --use-ue8m0

GLM tokens	Routed rows	Two-kernel (us)	Fused (us)	Speedup
1	8	16.623	10.264	1.62x
4	32	16.484	10.159	1.62x
16	128	16.579	10.237	1.62x
64	512	16.436	10.208	1.61x
128	1024	16.492	10.155	1.62x
256	2048	16.754	10.242	1.64x

The default DeepSeek-V4-style EP8 benchmark (top-k 6, hidden 2048) is 2.25-5.21x faster across 6-6144 routed rows after correcting both arms to apply the same expert filtering.

A wider CUDA-graph crossover sweep showed that unfiltered H=512 wins through 1M output elements but regresses beyond that point; the dispatch therefore falls back for larger prefills. Expert-filtered EP keeps the persistent kernel because skipping non-local rows dominates that crossover.

Matched GLM serving A/B

Configuration: 4x H200, TP4, MTP=5, BF16 KV cache, CUDA graphs, max batched tokens 8192, no tuned MoE config folder. Inputs and output lengths are fixed, temperature=0, ignore_eos, two warmup requests per run, and three measured runs per arm. The feature flag is the only implementation difference. All 576 measured requests succeeded. Values below are three-run medians.

Official recipe workload: 8192 input / 1024 output, concurrency 16, 64 requests

Metric	Baseline	Fused	Change
Output throughput	1176.43 tok/s	1206.74 tok/s	+2.58%
Total throughput	10587.85 tok/s	10860.70 tok/s	+2.58%
Mean TPOT	11.559 ms	11.244 ms	-2.72%
Median TPOT	10.425 ms	10.314 ms	-1.07%
Median TTFT	527.83 ms	586.67 ms	+11.15%
MTP acceptance	59.68%	63.08%	+3.40 pp

The output-throughput ranges were nearly non-overlapping: fused minimum 1191.30 tok/s versus baseline maximum 1190.24 tok/s. TTFT in the fused arm was noisy (516-637 ms) while baseline was 523-533 ms. Large prefills use the unchanged fallback, so no TTFT improvement is claimed.

Interactive workload: 512 input / 256 output, concurrency 16, 32 requests

Metric	Baseline	Fused	Change
Output throughput	1237.40 tok/s	1322.92 tok/s	+6.91%
Total throughput	3712.21 tok/s	3968.77 tok/s	+6.91%
Mean TPOT	10.376 ms	10.115 ms	-2.52%
Median TPOT	9.852 ms	9.952 ms	+1.01%
Median TTFT	323.20 ms	321.84 ms	-0.42%
MTP acceptance	52.24%	55.14%	+2.90 pp

MTP acceptance varies with scheduling, so the serving tables are reported together with the kernel and trace evidence rather than attributing every throughput point solely to kernel time.

An earlier same-architecture FP8 EP validation on 8x H200, TP8+EP8, Triton MoE, allgather_reducescatter, and 1024/128 c8 serving measured +7.31% output throughput, -6.72% mean TTFT, and -6.90% mean TPOT. This claim applies to the FP8 path, not the MXFP4/Marlin default of deepseek-ai/DeepSeek-V4-Flash-0731.

Correctness and validation

The regression grid covers hidden sizes 512 and 2048, 8/128/1024 routed rows, no filtering / IDs / expert map, and normal or UE8M0 scales. UE8M0 output bytes and scales must match the original clamped BF16-materialized path bit for bit; invalid and non-local rows remain untouched.

cmake --build cmake-build-pr32058 --target _C_stable_libtorch -j16
# linked successfully after rebasing onto upstream/main 4a6a3272e8

CUDA_VISIBLE_DEVICES=0 python -m pytest \
  tests/kernels/core/test_fused_silu_mul_block_quant.py -q
# 366 passed, 14 warnings

pre-commit run --from-ref origin/main --to-ref HEAD
# all applicable hooks passed

git diff --check origin/main...HEAD
# passed

The model-level evaluation is the matched serving A/B above. No separate accuracy benchmark is claimed; numerical equivalence to the original activation/quantization contract is enforced by the GPU regression tests.

Duplicate-work check

Open PR searches were run before implementation and refreshed before this update.

• [Perf][MoE] RTX 5090 Triton MoE optimizations: tuned config, fused SiLU+Mul+FP8 quant, unrolled topk sum #41915 is generic Triton work for unclamped models and does not provide this clamp + optional EP-filter CUDA specialization.
• reference SGLang PR #32058
• kernels: fused silu_and_mul + dynamic per-token FP8 quantization #49828 implements dynamic per-token FP8 quantization, not block-128 quantization.
• [Perf][Humming] Integrate fused SwiGLU FP8 quantization for W2 #53184 integrates a related fusion into the Humming backend, not TritonExperts.
• [MoE] Generalize masked activation for padded layouts #51217 generalizes masked activation layouts but does not fuse block quantization.
• Revert "[Perf] Wire silu_and_mul_per_block_quant into TritonFP8MoE (MiniMax-M2)" (#42497) #42973 concerns the existing generic unclamped wiring; this PR keeps that E8M0 path excluded and gates the new bit-exact clamped path.
• [Model] add GLM-5.3-Flash support #53906 adds GLM-5.3 model support but does not implement this kernel fusion.

AI assistance

AI assistance was used to profile, implement, benchmark, test, and draft this change. The human submitter reviewed every changed line, understands the implementation and validation, and is responsible for defending the change end to end.

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[AranKomat]

ROCm correctness evidence for the clamp guard in this PR: on gfx942 we reproduced the existing TritonExperts.apply fused SiLU/block128-FP8 branch bypassing a requested activation_config.clamp_limit. This matters independently of the new CUDA fusion.

Our native FP8/Triton expert-method diagnostic used E=8, top-k=6, H=5120, per-rank I=288 padded to384, seeds587/588, M=1/8/32 and low/high-amplitude inputs, with an independent decoded-original-weight, clamped FP32 oracle. The M1 clamp-active control had1076 clamp events and relative RMSE1.5703 / cosine0.85434. Requiring self.activation_config.clamp_limit is None for the existing unclamped fusion routed it through the existing activation fallback: that case became relative RMSE0.04542 / cosine0.99897; all12 cases passed the unchanged rRMSE<0.06/cosine>0.998 gates, including changed-input graph replay/allocator churn. These are quantized expert-method tolerances, not bitwise activation or model-quality claims.

Your condition clamp_limit is None or use_dsv4_fused_act_quant should preserve that fix on ROCm because the new specialized path is CUDA-gated. Would you consider splitting the generic correctness guard from the CUDA performance change so AMD users can receive it independently? Please retain a clamp-active ROCm dispatch regression; testing only the CUDA fused op would miss the original bug. This is supporting evidence for your existing PR, not a competing implementation. Investigation/testing and this note used Codex assistance.