[2/N][KV Connector][NIXL] Support per-region transfer geometry - #53780
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✅ Triggered Buildkite CI #85556 for commit |
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It seems there's way too many changes to core parts of the code here than I would have expected.
I need help understanding the flow we want to achieve here, because in my mental model right now we have to move the extra hot buffer in hbm but that shouldn't be redesigning so many parts of the code.
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This pull request has merge conflicts that must be resolved before it can be |
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No actionable comments were generated in the recent review. 🎉 ℹ️ Recent review info⚙️ Run configurationConfiguration used: Repository UI Review profile: CHILL Plan: Team Run ID: 📒 Files selected for processing (3)
🚧 Files skipped from review as they are similar to previous changes (1)
Included review availability: Your plan provides up to 10 included reviews per hour; 9 remain after this review. 📝 SummarySummary by CodeRabbit
WalkthroughNIXL now exchanges per-region block counts, group IDs, names, and memory types. Descriptor construction uses region-specific geometry. Pull transfers support mixed DRAM and device memory with deferred completion notifications. Push transfers reject mixed-memory caches. ChangesPer-region NIXL transfer geometry
Estimated code review effort: 4 (Complex) | ~60 minutes Merge Risk: ⚪ Minimal · up to NIXL transfers now carry and use per-region geometry for peers with different cache layouts. No concrete merge-blocking risk remains in the supplied current-head evidence. Sequence Diagram(s)sequenceDiagram
participant PullWorker
participant NixlConnectorWorker
participant NIXL
PullWorker->>NixlConnectorWorker: Build region-aware READ
NixlConnectorWorker->>NIXL: Submit DRAM and device descriptors
NIXL-->>NixlConnectorWorker: Complete transfer handles
NixlConnectorWorker->>PullWorker: Send notification after all reads finish
🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
✨ Finishing Touches 💡 1📝 Generate docstrings 💡
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Actionable comments posted: 3
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Inline comments:
In `@vllm/distributed/kv_transfer/kv_connector/v1/nixl/base_worker.py`:
- Line 1509: Update _build_local_splits_from_plan and its _fa_desc_replicated
call to construct split flags from each region’s self.region_num_blocks[i],
applying block_size_ratio per region instead of using the summed self.num_descs
value; preserve one flag per descriptor and add a regression test covering
unequal region capacities such as [2, 3].
In `@vllm/distributed/kv_transfer/kv_connector/v1/nixl/pull_worker.py`:
- Line 171: Update the logic around the single-source-rank assertion and
compute_tp_mapping to handle remote_info.remote_dcp_size > 1 when layouts
differ: apply region-aware DCP processing via _apply_dcp_prefix_caching, or
explicitly raise NotImplementedError before asserting one source rank. Preserve
the existing single-source-rank path for supported configurations.
In `@vllm/distributed/kv_transfer/kv_connector/v1/nixl/push_worker.py`:
- Around line 664-665: Update the PUSH handshake validation used by
_xfer_blocks_for_req to compare region_group_ids in addition to region count and
names, rejecting any mismatched layout before descriptor generation or transfer.
Ensure the compatibility check includes this field and add a regression test
covering differing group IDs, including equal-count layouts with unrelated
regions.
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tests/v1/kv_connector/unit/test_nixl_connector.pytests/v1/kv_connector/unit/test_nixl_connector_hma.pytests/v1/kv_connector/unit/test_nixl_desc_geometry.pytests/v1/kv_connector/unit/test_nixl_push_connector.pyvllm/distributed/kv_transfer/kv_connector/v1/nixl/base_worker.pyvllm/distributed/kv_transfer/kv_connector/v1/nixl/metadata.pyvllm/distributed/kv_transfer/kv_connector/v1/nixl/pull_worker.pyvllm/distributed/kv_transfer/kv_connector/v1/nixl/push_worker.pyvllm/distributed/kv_transfer/kv_connector/v1/nixl/tp_mapping.py
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Inline comments:
In `@tests/v1/kv_connector/unit/test_nixl_connector.py`:
- Line 1910: Initialize the NixlConnectorWorker test instance’s
_recving_metadata before invoking _pop_done_transfers with is_recv=True, so the
completed receive notification path can be exercised without AttributeError.
Keep the existing object.__new__ setup and transfer assertions unchanged.
In `@vllm/distributed/kv_transfer/kv_connector/v1/nixl/base_worker.py`:
- Line 1841: Update the mixed-memory path around _mixed_mem_types and
_needs_split_local_xfer_handles(...) so add_remote_agent splits each source’s
handle_data into separate DRAM and device handles before passing them to
get_xfer_descs(..., self.nixl_memory_type). Ensure _read_blocks_mixed uses
descriptor indices matching the device-only handle while DRAM reads use the
corresponding DRAM handle; alternatively reject this unsupported combination
explicitly.
In `@vllm/distributed/kv_transfer/kv_connector/v1/nixl/pull_worker.py`:
- Around line 174-176: Update the remote block handling in the region-mapped
ReadSpec path to expand logical meta.remote.block_ids through
_logical_to_kernel_block_ids before passing them to _block_ids_by_region when
remote_physical_blocks_per_logical is greater than one. Preserve the existing
behavior for matching granularity, or explicitly reject unsupported mismatched
ratios.
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tests/v1/kv_connector/unit/test_nixl_connector.pytests/v1/kv_connector/unit/test_nixl_desc_geometry.pyvllm/distributed/kv_transfer/kv_connector/v1/nixl/base_worker.pyvllm/distributed/kv_transfer/kv_connector/v1/nixl/pull_worker.py
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Left some comments to reduce scope of PR @MatthewBonanni :)
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Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Describe each transfer region's memory type, register DRAM and device descriptors separately, and defer producer notification until every split READ is terminal. Remove the coarse-to-fine region split geometry that matched HiSparse no longer needs. Co-authored-by: OpenAI Codex <codex@openai.com> Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Preserve CSA-linear region order and defer split READ failure reporting until all live handles are terminal. Co-authored-by: OpenAI Codex <codex@openai.com> Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: OpenAI Codex <noreply@openai.com> Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: OpenAI Codex <noreply@openai.com> Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Remove redundant validation and deferred failure handling now covered by the shared NIXL path, while retaining the mixed-memory completion barrier required before notifying the producer. Cache region-group mapping state to keep the read path cheap and cover failed mixed-memory reads. Co-authored-by: OpenAI Codex <noreply@openai.com> Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
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✅ Triggered Buildkite CI #87742 for commit |
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Resolve conflicts with per-region transfer geometry (vllm-project#53780): - _build_fa_local emits one run per region, or one run per block when a padded region is split by block_size_ratio (sub-blocks abut only inside a block, so a single stride cannot express the layout). - _build_fa_remote uses per-region block counts and strides. - Mixed DRAM/VRAM regions keep the per-descriptor desc_is_dram/desc_pos maps for the READ path; runs are partitioned per memory type by their first descriptor and _prep_xfer_dlist takes the memory type explicitly. - _use_strided_descs is a class attribute so skeleton workers built with object.__new__ in tests resolve it. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Signed-off-by: Ilia Yastrebov <iyastrebov@nvidia.com>
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Root cause: vllm#53780 added a per-region region_num_blocks list to NixlBaseConnectorWorker and made _build_fa_local index it (self.region_num_blocks[i]). The HPU register_kv_caches override (hpu_nixl_connector.py) never populated that list, so the first index access raised IndexError on every NIXL PD job. Upstream: vllm-project/vllm#53780 Fix: append the per-region block count in the same loop that already populates block_len_per_layer/block_stride_per_layer, extend the region-count consistency assert, and mirror upstream's Mamba/hybrid-SSM override of region_num_blocks to the physical block count. Signed-off-by: Paweł Olejniczak <pawelx.olejniczak@intel.com>
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…te per-region NIXL registration bookkeeping Root cause: vllm#53780 made the NIXL memory type, transfer group and name per-region, and register_local_xfer_handler now reads region_mem_types[0]; the HPU register_kv_caches override (a pre-#44456 copy kept to restore the K/V region split) never populated any of those lists, so every NIXL PD engine died with IndexError at KV cache registration. Upstream: vllm-project/vllm#53780 Fix: append region_mem_types / region_group_ids / region_names per region in the override's registration loop, derive _mixed_mem_types and _uses_region_group_mapping from them, and publish the local engine's dst_region_* geometry, matching upstream's post-#53780 tail. Signed-off-by: Paweł Olejniczak <pawelx.olejniczak@intel.com>
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…project#53780) Signed-off-by: Matthew Bonanni <mbonanni@redhat.com> Co-authored-by: OpenAI Codex <codex@openai.com> Co-authored-by: OpenAI Codex <noreply@openai.com> Signed-off-by: Jyotirmoy Roy <jyotirmoyroy649@gmail.com>
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…emoved actorder/g_idx, populate region_num_blocks in (+3 more) (#1788) This PR consolidates 5 hourly-CI fixes against vllm@`d2906091bfc579cebefe3d8e8fb9077397ce9882`. ## Bug 1: drop removed actorder/g_idx kwargs from HPU WNA16 scheme - **State machine id**: compressed_tensors_wna16_actorder_no_longer_supported - **Commit**: 9b4b363 ### Root cause vllm#54809 removed GPTQ group/dynamic activation ordering support, deleting the actorder ctor kwarg, has_g_idx attribute, and weight_g_idx/w_gidx_param_name plumbing from CompressedTensorsWNA16 and MPLinearKernel. HPUCompressedTensorsWNA16 in vllm_gaudi/ops/hpu_compressed_tensors.py still passed/read those removed names, so every WNA16 checkpoint load hit TypeError before reaching the kernel. ### Culprit Regression introduced by [PR #54809](vllm-project/vllm#54809). ### Fix drop actorder/has_g_idx/w_gidx_param_name from the HPU WNA16 scheme and kernel, matching upstream's removal; retire the compressed_w4a16 MoE g_idx e2e job since its checkpoint declares actorder=group, which vLLM now rejects on every backend before hardware dispatch. ## Bug 2: populate region_num_blocks in HPU NIXL KV-cache registration - **State machine id**: nixl_pd_build_fa_local_region_num_blocks_indexerror - **Commit**: 0f8b433 ### Root cause vllm#53780 added a per-region region_num_blocks list to NixlBaseConnectorWorker and made _build_fa_local index it (self.region_num_blocks[i]). The HPU register_kv_caches override (hpu_nixl_connector.py) never populated that list, so the first index access raised IndexError on every NIXL PD job. ### Culprit Probable culprit: [PR #53780](vllm-project/vllm#53780) — pinned by symbol archaeology, bisect not run. Candidate range: [compare](vllm-project/vllm@cd64c2d...d290609). ### Fix append the per-region block count in the same loop that already populates block_len_per_layer/block_stride_per_layer, extend the region-count consistency assert, and mirror upstream's Mamba/hybrid-SSM override of region_num_blocks to the physical block count. ## Bug 3: register HPU Pixtral lazily - **State machine id**: opt_causal_lm_modelconfig_inspect_validation_error - **Commit**: c41afcd ### Root cause transformers 5.17.0 removed PixtralRotaryEmbedding and position_ids_in_meshgrid, so the eager Pixtral import in register_model() aborted plugin registration for every architecture. ### Culprit Regression introduced by [PR #48105](huggingface/transformers#48105). ### Fix drop the redundant eager import and keep only the lazy "module:class" registration. ## Bug 4: populate per-region NIXL registration bookkeeping - **State machine id**: nixl_register_local_xfer_region_mem_types_indexerror - **Commit**: 4ec533f ### Root cause vllm#53780 made the NIXL memory type, transfer group and name per-region, and register_local_xfer_handler now reads region_mem_types[0]; the HPU register_kv_caches override (a pre-#44456 copy kept to restore the K/V region split) never populated any of those lists, so every NIXL PD engine died with IndexError at KV cache registration. ### Culprit Regression introduced by [PR #53780](vllm-project/vllm#53780). ### Fix append region_mem_types / region_group_ids / region_names per region in the override's registration loop, derive _mixed_mem_types and _uses_region_group_mapping from them, and publish the local engine's dst_region_* geometry, matching upstream's post-#53780 tail. ## Bug 5: cap transformers below 5.17 - **State machine id**: mistral3_pixtral_rotary_embedding_import_error - **Commit**: 1e9da63 ### Root cause transformers 5.17.0 removed position_ids_in_meshgrid and renamed PixtralRotaryEmbedding to PixtralVisionRotaryEmbedding, both imported at module level by upstream vLLM's vllm/model_executor/models/pixtral.py, so PixtralForConditionalGeneration can no longer be inspected. ### Culprit Regression introduced by [PR #48105](huggingface/transformers#48105). ### Fix cap transformers<5.17, the version upstream vLLM tests against, until vLLM adopts the new vision rotary-embedding API. --------- Signed-off-by: Paweł Olejniczak <pawelx.olejniczak@intel.com>
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Summary
This is the generic geometry prerequisite needed before HiSparse can transfer long-context host regions safely.
Duplicate check
#50717 is a draft limited to packed-cache block-size synchronization. #51527 is a draft targeting heterogeneous P/D logical block sizes. Neither provides the general per-region metadata, packed registration, group mapping, and descriptor geometry in this PR. The HiSparse stack needs that common substrate independently.
Tests
source .venv/bin/activate python -m pytest tests/v1/kv_connector/unit/test_nixl_desc_geometry.py -q python -m pytest tests/v1/kv_connector/unit/test_nixl_connector_hma.py tests/v1/kv_connector/unit/test_nixl_connector.py tests/v1/kv_connector/unit/test_nixl_push_connector.py -m cpu_test -qResults: 200 passed for descriptor geometry; 70 passed and 125 deselected for the broader CPU NIXL selection. Changed-file pre-commit hooks passed.
Model evaluation
Not applicable: this changes transfer descriptors and validation. The dependent HiSparse PR contains the end-to-end model and performance evaluation.
AI assistance
AI assistance was used for implementation, tests, review, and documentation. The human submitter is responsible for reviewing every changed line and defending the change end-to-end.