[Kernel][PCP] Publish replicated KV updates through PyTorch symmetric memory

[foraxe]

Summary

Replace the PCP KV-update AllGather with direct publication of final quantized Main-KV and Indexer-K rows into each replicated cache through PyTorch SymmetricMemory. The symmetric-memory domain is owned by the KV-cache lifecycle, scoped to the runtime PCP group, and uses one capture-safe release/acquire barrier after publication.

The gather path remains the fallback. Direct KV is selected automatically when the CUDA PCP topology and attention layers support it. Set VLLM_USE_PCP_DIRECT_KV=0 to disable it; 1 requests it and warns if the configuration is unsupported.

AS-IS: gather then insert

  local final K/V rows
          |
          v
  PCP AllGather of update tensors
          |
          v
  each rank inserts gathered rows
          |
          v
  replicated local KV cache

THIS PR: publish final rows directly

  local final K/V rows
          |
          +---- store to PCP peer cache 0
          +---- store to PCP peer cache 1
          +---- store to PCP peer cache N
          |
          v
  system-scope release/acquire barrier
          |
          v
  replicated local KV cache

  no KV-update AllGather
  no receive-side cache insertion

The cache layout and capacity are unchanged. Existing attention kernels still consume ordinary local cache tensors.

Design

• KVCache owns the backing storage, peer views, rendezvous handles, and teardown.
• The PCP domain is built from the runtime PCP device group; TP2/PCP2 therefore publishes independently within each same-TP PCP subgroup.
• Fused DeepSeek/GLM cache-store kernels write the final FP8 Main-KV and Indexer-K bytes to every PCP peer pointer.
• A device-epoch barrier provides system-scope publication and supports CUDA Graph replay and separate DBO lanes.
• Sparse-MLA PIECEWISE CUDA Graphs are supported when direct KV is selected.
• Full-graph modes remain gated. In particular, rank-divergent PCP prefill replay is not claimed by this PR.
• Dense or masked-MHA fallbacks retain the local normalized/rotated K outputs they require.

The lifecycle refactor from foraxe/vllm#4 also removes the gpu_worker.py teardown hook and the lazy PCP/direct-KV imports previously used by init_kv_cache.

Correctness and current-head validation

Validated after merging current vLLM main at 12b9573c98:

• tests/v1/worker/test_gpu_pcp_manager.py
• tests/v1/worker/test_kv_cache_allocation_scope.py
• tests/v1/worker/test_utils.py
• tests/v1/worker/test_gpu_model_runner_v2_cudagraph_profiling.py
  • Result: 35 passed.
• tests/distributed/test_pcp_symm_kv.py on 4x GB200
  • Result: 16 passed.
  • Covers PCP2, PCP4, TP2/PCP2, FP8/fp8_ds_mla, padded and invalid slots, guard bytes, lifecycle teardown, and captured barrier replay.
• Ruff format/check on all 19 changed Python files: passed.
• Pre-commit on all changed files, including mypy: passed.
• git diff upstream/main --check: passed.

The current direct path remains byte-exact against gather-then-insert oracles before timing.

Performance evidence

The engine data below was collected earlier on this PR before the lifecycle/CUDA-Graph refactor. It is retained as evidence for the same direct-final data path, but it was not rerun for the current head.

Same-source 10-pair cold-start A/B on 4x GB200, GLM-5.2 NVFP4, TP1/PCP4/DCP1, eager, FP8 KV, prefix caching off. Only direct KV was changed; ordering was counterbalanced AB/BA, and all 40 result JSONs completed.

Workload	Mean TTFT	Mean TPOT	Request throughput
1,024 input / 32 output, c16	-12.64%	-2.66%	+3.83%
3,584 input / 32 output, c4	-13.05%	-3.03%	+3.87%

KV capacity was unchanged at 706,624 tokens on both arms. These percentages are not combined with other PRs or operator measurements.

Scope and fallback

In scope:

• Single-node NVIDIA PCP for supported DeepSeek/GLM sparse-MLA layers.
• Replicated Main-KV and Indexer-K updates.
• PCP2, PCP4, and TP2/PCP2 subgroup operation.
• Eager and PIECEWISE CUDA Graph execution.

Not claimed:

• Owner-sharded historical KV capacity.
• Direct TP replication.
• Multi-host PCP.
• Full-graph PCP prefill.

If direct KV is disabled or unsupported, vLLM retains the existing gather-and-insert path.

Relationship to existing work

• #52046 is the gather-and-insert baseline used by the fallback path.
• #49517 introduced the direct-final replicated-KV idea using CUDA VMM.
• This PR uses PyTorch SymmetricMemory and a KV-cache-owned lifecycle instead of a custom VMM allocator.
• foraxe/vllm#4 supplied the group-scoped lifecycle and CUDA-Graph-safe refactor merged into this branch.

Implementation and validation used AI coding assistance. The human submitter reviewed the changed lines, selected the validation gates, and owns the claims above.

Co-authored with @GirasoleY.
Co-authored with @taoyuanyuan.

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[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @foraxe.

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[foraxe]

@WoosukKwon @LucasWilkinson @GirasoleY could you take a look at this PCP KV-update path?

It ports the direct-final idea from #49517 onto merged PyTorch SymmetricMemory:

producers write the final quantized Main-KV / Indexer-K rows into every replica and
skip the #52046 AllGather+insert. Opt-in (VLLM_USE_PCP_DIRECT_KV=1).

On GLM-5.2 TP1/PCP4, same-source 10-pair A/B:

• TTFT -12.6% / -13.1%,
• TPOT slightly improved, KV capacity unchanged.

Happy to walk through the hook / slot-row / fail-closed bits.

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[foraxe]

I have a follow-up extending this design from TP1 to TP>1. Hi @GirasoleY, could you please take a look at the subgroup-scoped design?

Direct-final KV publication remains scoped to the existing PCP process group. With TP2/PCP2, vLLM creates two independent PCP publication domains, each containing ranks with the same TP coordinate. Symmetric-memory allocation, peer pointers, stores, and release/acquire publication therefore never cross TP shards. The test uses vLLM's actual model-parallel group construction rather than hard-coded rank lists.

Validation on 4x GB200:

• TP2/PCP2 FP8 Main-KV and Indexer-K byte oracle passed.
• All PCP-group members were verified to share the same TP coordinate.
• One same-source cold AB engine screen completed with zero failed requests.
• Preliminary TTFT change was +0.13% at 1K input/concurrency 16 and -9.60% at 3584 input/concurrency 4. This is early single-pair evidence, not a statistical performance claim.
• KV capacity remained identical at 910,336 tokens.

[mergify]

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merged. Please rebase the PR, @foraxe.

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[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @foraxe.

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[GirasoleY]

Thanks for the support, functionality this is good, I added one refactor PR, if you find this make sense feel free to merge this into the PR.

foraxe#4

KvCache:
    storage  # one symmetric-memory backing allocation
    tensors  # shaped per-layer views
    pcp_domain: KVCacheSymmMemDomain
    tp_domain

• generalize direct pcp kv to a direct kv implementation that works for both pcp/tp group
• refactor KvCache to work with both symm-mem / local torch storage
• use one backing storage with independent PCP and future TP/DCP rendezvous handles (different group can exchange the storage independently)
• gate: change to auto | 1 | 0 - auto-select direct KV when supported while retaining the PCP gather fallback
• support CUDA graphs and DBO barrier lanes, and simplify the kernel/view/barrier wiring

[GirasoleY]

Overall the change looks good!

Since this touches KvCache it will conflict with the ongoing expandable kv cache change in #50779

#50779 is a more foundational change, my current preference is to hold this until it lands, and rework after: #50779 keeps a stable VA but might change the underline PA based on available kv cache after graph capture. So instead of relying on torch symmem to allocate buffer, we'll have to build our own rendezvous() method to exchange the handle.

cc. @njhill

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This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @foraxe.

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