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GB10 silicon log (single-node, synthetic)Draft update: ran the Triton fallback on a live DGX Spark (NVIDIA GB10, compute capability (12, 1)) inside official Same window, same image: Qwen2.5-VL-3B served on that GB10 ( This is the o_proj / |
Port jasl SM12x Triton fp8_einsum; dispatch from o_proj with a per-kernel predicate (capability, equation, recipe, scale dtype). SM12x uses the SM90-shaped (1, 128, 128) recipe instead of SM100 (1, 1, 128) which asserts in DeepGEMM layout.hpp on GB10 / RTX 50. Does not enable support_deep_gemm() for family-120. Refs: #43743 #41834 Signed-off-by: Andrew Wharton <ajwharton@gmail.com>
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DCO should be green on
GB10 silicon log is in the previous comment. |
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Field report from 2x DGX Spark GB10 (SM 12.1), TP=2,
This PR's SM12x recipe On this box Triton Happy to re-test this branch on the same pair if useful. |
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End-to-end GB10 follow-up on current head I used this PR's two runtime files byte-for-byte in a vLLM 0.27.1 adaptation:
The serving test was 2× DGX Spark / GB10 (SM121), TP=2, with an FP4 DeepSeek-V4-Flash-0731 checkpoint, MXFP4 B12X experts, FlashInfer sparse MLA, NVFP4 DS-MLA KV, probabilistic DSpark k=5, 532,288 max context, and CUDA graphs. The full model loaded 79.48 GiB per rank, allocated 746,430 KV tokens, completed sparse-MLA autotuning and graph capture, and reached API readiness. A six-part functional run passed model listing, thinking-off, reasoning, exact tool-call JSON, streaming, and 48,033-token retrieval. Both ranks remained restart-zero and OOM-free, with no Xid, CUDA/NCCL fatal, Scope note: this validates the two runtime files from this PR as part of a complete SM12x serving stack, not the PR's test file or a standalone cherry-pick. Additional SM12x MHC/MQA and FlashInfer sparse-MLA shape fixes were also required for the full serve. |
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Closing this draft. Decision made 2026-08-23: upstream vLLM is continuing down the SM12x/DeepGEMM path on its own, so this fork-side Triton-fallback slice is no longer worth maintaining. The commit (and full fork history) is preserved in a local bundle. Thanks to jasl/#41834 and #43743 for the groundwork — we'll pick this up through official channels when it matures. |
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Main still takes the SM100 packed-INT32 recipe whenever Recipe-only follow-up: #53521 |
Compiled DeepGEMM einsum asserts m/n/k on GB10. Keep the Hopper (1, 128, 128) recipe and dispatch o_proj to the vllm-project#52357 Triton fallback. Do not Marlin/Humming-pack is_bmm wo_a weights. Co-authored-by: Cursor Grok 4.6 Signed-off-by: Cursor Agent <cursoragent@cursor.com>
Purpose
Fixes #43743.
We're trying to intuit where you are already going on SM12x / GB10 and help
out with a small, reviewable slice — not a parallel stack.
On current
main, DSv4o_projalways calls DeepGEMMfp8_einsum.compute_fp8_einsum_recipe()treatscap.major >= 10as the SM100(1, 1, 128)layout. GB10 / RTX 50 report major=12, so they take thatrecipe and die on the first forward (
layout.hppscale-factor assert —the same class as "Unknown SF transformation").
#41834 already fixed
tf32_hc_prenorm_gemm. This PR is the follow-uppasta-paul described in #43743: port jasl's Triton SM12x
fp8_einsumfallback and dispatch it with a per-kernel predicate (capability,
equation, recipe, scale dtype), not
support_deep_gemm() |= family(120).That last point is deliberate. We tried the blunt family-120 DeepGEMM
enable on a dual GB10 box; MoE selected
DEEPGEMM_MXFP4, then linearo_projhitlayout.hpp:97. The gate comment onCudaPlatformwasright. This PR does not open that gate.
What this does / does not
Does:
(1, 128, 128)+ Triton fallbackSM100 recipe
Does not:
Attribution
predicates, not architecture-family assumptions)
We are integrators/validators on GB10 (DGX Spark). Draft while we attach
a silicon log from a single-node sm_121 probe (synthetic o_proj tensors;
no 156G load). Happy to adjust the predicate or split the kernel file if
that's a better fit for how you want this to land.
Test Plan
GB10 kernel probe (synthetic
bhr,hdr->bhd, recipe(1,128,128)) stillin flight — will comment the log on this PR.
Test Result
Dispatch tests exist; not yet run in CI. Silicon evidence forthcoming.