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Improve low-batch long-context split-K parallelism, compile cache geometry into the Triton kernels, decode UE8M0 scales with exponent bits, and write directly to the caller output. Add production-shape coverage for 8192 selected KV rows and split count 32. Assisted-by: OpenAI Codex Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
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/ci run |
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✅ Triggered Buildkite CI #83840 for commit |
Pull request was converted to draft
Use an in-tree Gluon-style gfx950 kernel with shared-LDS KV reuse, explicit MFMA layouts, pipelined gathers, direct S1 output, and reusable split-K scratch. Preserve the existing Triton kernels on other architectures. Validate eager and graph parity against the corrected AITER Gluon implementation across batch and long-context shapes. Assisted-by: OpenAI Codex Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
This reverts commit 38ef980. Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
Add a gfx950-only standard Triton sparse-decode partial specialization with improved QK/PV dataflow, workload-aware split selection, and trusted NaN-free compressed-cache handling. Preserve the standard gfx942 and generic paths and the existing reducer. Assisted-by: OpenAI Codex Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
Broaden the gfx950 split policy across T=16-48 so short, mid, and long contexts retain the same modeled occupancy without excess reducer work. Extend the focused policy test with representative one- and two-wave cases. Assisted-by: OpenAI Codex Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
Under the same 8× MI355X TP8/EP1, c32, 1200s, warmup=10, and FSE-enabled setup, Triton and AITER Gluon are effectively tied, with Triton delivering 0.25% higher throughput. |
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This pull request has merge conflicts that must be resolved before it can be |
8k/1k TP8 follow-upI reran the canonical 8k/1k serving workload after addressing the two issues
The follow-up is now pushed in Configuration
The 640-element input/output length arrays were byte-identical between arms For a fair comparison, the reference is exact old source
Both arms completed 640/640 scored requests and 768/768 total requests Result JSON SHA-256: reference The local follow-up is also +0.808% in output throughput versus the retained Kernel/correctness validation
The full-model numbers above are one fresh paired run per arm, so I am treating AI assistance was used for the patch implementation, test development, and |
Resolve the compressor test conflict by retaining both the gfx950 helper and the upstream DSpark SWA width coverage. Assisted-by: OpenAI Codex Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
Adapt captured sparse-decode work to live ragged lengths and avoid per-shape cp-gather compilation on gfx950. Preserve the legacy selector, kernels, and launch specialization on other ROCm architectures. Assisted-by: OpenAI Codex Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
Remove the one-off benchmark extension and redundant private-layout tests. Reuse the loaded-tile helper in the gfx950 partial kernel while preserving graph replay and stale-scratch coverage. Assisted-by: OpenAI Codex Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
vllm-project#51430/vllm-project#51768 moved DSV4 to MRV2 and a narrow eager region. That is a large decode TPOT regression on ROCm. Default ROCm back to MRV1, wrap the full attention body in the eager break for MRV1 only, and drop the MRV1+PIECEWISE rejection. CUDA keeps MRV2 and the narrow region. Co-authored-by: Nick Hill <nickhill123@gmail.com> Co-authored-by: Cursor Grok 4.6 <cursoragent@cursor.com> Signed-off-by: fai <fangzhouai@gmail.com>
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✅ Triggered Buildkite CI #84060 for commit |
…project#52212) Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com> Signed-off-by: fai <fangzhouai@gmail.com> Co-authored-by: Nick Hill <nickhill123@gmail.com> Co-authored-by: Cursor Grok 4.6 <cursoragent@cursor.com>
…project#52212) Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com> Signed-off-by: fai <fangzhouai@gmail.com> Co-authored-by: Nick Hill <nickhill123@gmail.com> Co-authored-by: Cursor Grok 4.6 <cursoragent@cursor.com> Signed-off-by: Wyett <wyettzeng@gmail.com>
…project#52212) Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com> Signed-off-by: fai <fangzhouai@gmail.com> Co-authored-by: Nick Hill <nickhill123@gmail.com> Co-authored-by: Cursor Grok 4.6 <cursoragent@cursor.com> Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
…project#52212) Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com> Signed-off-by: fai <fangzhouai@gmail.com> Co-authored-by: Nick Hill <nickhill123@gmail.com> Co-authored-by: Cursor Grok 4.6 <cursoragent@cursor.com> Signed-off-by: khushali9 <khushali.desai9@gmail.com>
Summary
Optimize the existing in-tree Triton DeepSeek-V4 sparse-MLA decode path for
gfx950/MI355X.
The change adds a dedicated gfx950 partial kernel, workload-aware split
selection, graph-safe adaptive work selection, and gfx950-only cp-gather
de-specialization. It adds no AITER/Gluon runtime dependency or implementation
switch; corrected AITER/Gluon is used only as a performance comparator.
The PR remains draft while refreshed CI runs and the human submitter completes
the final line-by-line review.
gfx950-only scope
All new runtime behavior is explicitly gated by
_ON_GFX950:gfx942 retains its existing 1-16 split selector, partial/ragged kernels,
cp-gather specialization, reducer behavior, and output path. A read-only gfx942
AOT audit found byte-identical HSACO text versus the clean baseline.
Design
The gfx950 kernel:
The split selector targets device occupancy, caps short workloads at four
splits, and uses up to 32 splits for low-batch long-context rows.
Compressed-cache scrub elision requires an explicit, false-by-default
provenance bit. On gfx950, both writers cap UE8M0 codes at 254 and canonicalize
RoPE NaNs. Main-cache values are still scrubbed, invalid indices contribute
zero probability, and cache block address multiplication uses int64.
Performance
Kernel acceptance
On one 256-CU MI355X, the exact 40-shape matrix
T={1,2,4,8,16,32,48,64} x context={4K,32K,100K,500K,1M}passed eager andwarmed-graph correctness and the
<=1.03performance gate:All 1,920 correctness comparisons passed with
atol=rtol=0.02.The final source-only cleanup was rechecked on four representative graph
shapes. Outputs were bitwise identical, p50 changed by -0.15% to +0.18%, and
the S8/S32 executable text and resource usage were unchanged.
Canonical 8k/1k serving A/B
Configuration: 8x MI355X, TP8/DP1, concurrency 64, prefix caching disabled,
128 warmups followed by 640 scored requests, and fresh isolated compile caches.
The reference used the exact old sparse-decode source plus the same cp-gather
fix as the candidate. Input/output length arrays were byte-identical.
Both arms completed all requests without errors, preemption, or prefix-cache
activity. Every reported P99/P99.9 latency improved; P90 TTFT was the sole
regressed percentile. This is a positive paired no-regression result, not a
claim of statistical consistency from one run per arm.
Full results and methodology are in the
8k/1k follow-up comment.
Validation
Results on the current head: 57 attention tests passed, four focused
compressor/cp tests passed, all changed-file pre-commit hooks passed, and
Python 3.12 mypy passed.
A full GSM8K run on the preceding pure-Triton source completed all 1,319
examples with strict accuracy 0.960576 and flexible accuracy 0.959818.
Duplicate-work check
Issue #41820 and open PRs were checked for
41820 in:bodyandDSV4 sparse MLA Triton. No open PR duplicates this change. #50566 focuses onreusable split-K scratch and output-copy removal; #51714 adds an optional
external AITER/Gluon path. This PR instead optimizes the default in-tree Triton
implementation on gfx950.
AI assistance and accountability
OpenAI Codex assisted with investigation, implementation, test development,
benchmarking, auditing, and drafting. The human submitter remains responsible
for reviewing every changed line, understanding and defending the change,
rerunning the relevant tests, and completing final CI review.