[Kernel] Add FlashInfer TRTLLM MXFP8 linear backend by seonjinn · Pull Request #52204 · vllm-project/vllm

seonjinn · 2026-08-13T18:38:57Z

Purpose

FlashInfer exposes a TensorRT-LLM backend for dense MXFP8 GEMM, but vLLM's
flashinfer_trtllm linear selector currently covers NVFP4 only. This change
adds FlashInferTrtllmMxfp8LinearKernel, which can be selected with:

--linear-backend flashinfer_trtllm

The kernel prepares TensorRT-LLM weight and scale layouts once after weight
loading. At runtime it quantizes BF16 activations with the 8x4 scale layout,
calls FlashInfer's TensorRT-LLM MXFP8 GEMM, and slices the physically padded
output back to its logical width before adding bias.

The kernel is the last CUDA entry in the MXFP8 priority list, so existing
kernels retain their normal priority. Explicit flashinfer_trtllm selection
filters the list to this kernel. This PR does not add tactic hints, MoE kernel
changes, or the high-M 128x4 activation-scale path.

No matching open PR was found with the searches MXFP8 TRTLLM linear and
mm_mxfp8 trtllm. The closest merged implementations are the NVFP4 TRTLLM
linear backend (#39129) and the MXFP8 CuTeDSL linear backend (#46393). Open PR
#52016 adds the independent B12X CuTeDSL package for SM120/SM121 and does not
expose FlashInfer's TensorRT-LLM MXFP8 runner.

Test Result

.venv/bin/python -m pytest --confcutdir=tests/kernels/quantization \
  tests/kernels/quantization/test_mxfp8_trtllm_linear.py -q

1 passed

.venv/bin/pre-commit run --files \
  docs/features/quantization/modelopt.md \
  tests/kernels/quantization/test_flashinfer_mxfp8_trtllm.py \
  tests/kernels/quantization/test_mxfp8_trtllm_linear.py \
  vllm/model_executor/kernels/linear/__init__.py \
  vllm/model_executor/kernels/linear/mxfp8/flashinfer.py

All hooks passed

The GB200 test passed five real-GPU cases: three numerical shapes with M=1,
7, and 128, custom-op checks, and CUDA Graph capture and replay. The N=130
cases cover physical output padding and slicing. The run used commit
37d19a7edd7559c3f8da24703d53feea198f96b4 and FlashInfer 0.6.16.post3,
matching the vLLM dependency pin. Model-level accuracy and same-version
performance results are not yet available, so this PR makes no accuracy or
performance claim.

github-actions · 2026-08-13T18:39:09Z

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claude

Claude Code Review

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seonjinn · 2026-08-13T18:41:14Z

@claude review

mergify · 2026-08-13T18:53:06Z

Documentation preview: https://vllm--52204.org.readthedocs.build/en/52204/

Expose the TRTLLM MXFP8 dense GEMM path behind the existing flashinfer_trtllm linear backend selector. Prepare weights and scales once at load time, preserve the actual activation row count, and restore logical output dimensions after physical N padding. Assisted-by: OpenAI Codex Signed-off-by: seonjinn <sna@nvidia.com>

claude

Claude Code Review

This pull request is from a fork — automated review is disabled. A repository maintainer can comment @claude review to run a one-time review.

…m-linear-main Signed-off-by: seonjinn <sna@nvidia.com>

mgoin · 2026-08-19T18:11:35Z

    `vllm serve --help=KernelConfig`.

+!!! note
+    For MXFP8 checkpoints on SM100, SM103, and SM107 GPUs, BF16 models can


Do you mean "MXFP8 models"?

Updated to "models quantized to MXFP8 with BF16 activations" to distinguish the weight format from the activation dtype.

mgoin · 2026-08-19T18:13:38Z

-    possible = list(_POSSIBLE_MXFP8_KERNELS.get(platform, []))
+    possible = [
+        kernel
+        for kernel in _POSSIBLE_MXFP8_KERNELS.get(platform, [])
+        if kernel is not FlashInferTrtllmMxfp8LinearKernel
+    ]
+
+    if _get_linear_backend() == "flashinfer_trtllm":
+        possible.append(FlashInferTrtllmMxfp8LinearKernel)


Maybe you could add it to the bottom of _POSSIBLE_MXFP8_KERNELS if you don't want this chosen by default? I'd prefer to not have a special case

Done. The kernel is now the last CUDA MXFP8 candidate, and the special-case selection logic is removed.

mgoin · 2026-08-19T18:14:15Z

+        if x.dtype != torch.bfloat16:
+            raise ValueError(
+                "FlashInfer TRTLLM MXFP8 requires bfloat16 output, "
+                f"got input dtype {x.dtype}."
+            )


nit: assert

Done. Replaced the BF16 dtype ValueError with an assertion.

mgoin · 2026-08-19T18:16:13Z

+        weight = layer.weight  # shuffled [padded N, K]
+        weight_scale = layer.weight_scale
+        _, K = weight.shape
+        output_size = layer._mxfp8_trtllm_output_size
+        input_shape = x.shape
+        input_2d = x.view(-1, K)
+
+        input_mxfp8, input_scale = vllm_flashinfer.flashinfer_mxfp8_quantize_8x4(
+            input_2d
+        )
+        output = vllm_flashinfer.mm_mxfp8(
+            input_mxfp8,
+            weight.t(),
+            input_scale,
+            weight_scale,
+            out_dtype=x.dtype,
+            backend="trtllm",
+            use_8x4_sf_layout=True,
+        )
+        if output.shape[-1] != output_size:
+            output = output[:, :output_size].contiguous()


Are we missing padding the input to match the weight?

No input padding is needed. Only N is padded, so the operands remain A[M, K] and B[K, padded_N]; the result is sliced back to N. The 8x4 quantizer handles M-side scale-layout padding internally.

mgoin · 2026-08-19T18:16:59Z

+        if compute_capability is None:
+            supported_capability = any(
+                current_platform.is_device_capability(capability)
+                for capability in (100, 103, 107)
+            )
+        else:
+            supported_capability = compute_capability in (100, 103, 107)
+        if not supported_capability:
+            return False, "requires sm_100/sm_103/sm_107 (Blackwell)"


nit: can just do current_platform.is_device_capability_family(100)

Done. The kernel and its GPU test now use the SM100-family capability helper.

mgoin · 2026-08-19T18:18:20Z

I think a lot of these mocked tests are overkill

I removed this part

Reduced the mocked CPU suite from 252 lines to one backend-selection test. Numerics, padding, custom-op checks, and CUDA Graph coverage remain in the real GPU tests.

Signed-off-by: seonjinn <sna@nvidia.com>

Signed-off-by: Misha Goin <mgoin64@gmail.com>

mgoin

LGTM thanks!

mgoin · 2026-08-19T19:36:44Z

/ci run

github-actions · 2026-08-19T19:36:48Z

✅ @seonjinn, CI is now available for this PR.

/ci run starts upstream CI; /amd-ci run starts AMD CI only.
/ci retry retries failed jobs in the CI build for the current PR head. If the current head has no CI build, it starts a new CI build for the current head containing only jobs that failed in the latest earlier CI build for this PR.
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/ci cancel cancels scheduled or running CI builds for this PR branch; /amd-ci cancel does the same for AMD CI only.

github-actions · 2026-08-19T19:37:02Z

✅ Triggered Buildkite CI #84669 for commit eb2b0e0f8b78.

mergify · 2026-08-19T19:37:37Z

Hi @seonjinn, the pre-commit checks have failed. Please run:

uv pip install pre-commit>=4.5.1
pre-commit install
pre-commit run --all-files

Then, commit the changes and push to your branch.

For future commits, pre-commit will run automatically on changed files before each commit.

Signed-off-by: seonjinn <sna@nvidia.com>

mgoin · 2026-08-19T20:37:43Z

/ci run

github-actions · 2026-08-19T20:38:01Z

✅ Triggered Buildkite CI #84684 for commit ec8978934cf2.

seonjinn · 2026-08-20T00:26:10Z

@mgoin For amd-mi300-v1-spec-decode test case, does it take longer time usually?

Signed-off-by: seonjinn <sna@nvidia.com> Signed-off-by: Misha Goin <mgoin64@gmail.com> Co-authored-by: Misha Goin <mgoin64@gmail.com> Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>

Signed-off-by: seonjinn <sna@nvidia.com> Signed-off-by: Misha Goin <mgoin64@gmail.com> Co-authored-by: Misha Goin <mgoin64@gmail.com>

mergify Bot added the nvidia label Aug 13, 2026

github-project-automation Bot added this to NVIDIA Aug 13, 2026

seonjinn marked this pull request as ready for review August 13, 2026 18:40

seonjinn requested review from AndreasKaratzas, WoosukKwon, mgoin, tlrmchlsmth, yewentao256 and zyongye as code owners August 13, 2026 18:40

claude Bot reviewed Aug 13, 2026

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seonjinn marked this pull request as draft August 13, 2026 18:43

seonjinn force-pushed the feature/mxfp8-trtllm-linear-main branch from 8f90950 to d7c8714 Compare August 13, 2026 18:52

mergify Bot added the documentation Improvements or additions to documentation label Aug 13, 2026

seonjinn force-pushed the feature/mxfp8-trtllm-linear-main branch from d7c8714 to 37d19a7 Compare August 13, 2026 18:58

This was referenced Aug 14, 2026

feat(vllm): support refit-safe MXFP8 linear backends NVIDIA-NeMo/RL#3638

Open

[Kernel] Add adaptive layouts to TRTLLM MXFP8 linear backend #52275

Open

LH-and-FPGA mentioned this pull request Aug 17, 2026

[Bugfix][Quantization] Guard the MXFP8 FlashInfer path on FlashInfer availability #52648

Merged

seonjinn marked this pull request as ready for review August 18, 2026 21:30

claude Bot reviewed Aug 18, 2026

View reviewed changes

Merge remote-tracking branch 'upstream/main' into feature/mxfp8-trtll…

b82e145

…m-linear-main Signed-off-by: seonjinn <sna@nvidia.com>

mgoin reviewed Aug 19, 2026

View reviewed changes

seonjinn and others added 3 commits August 19, 2026 11:49

Address MXFP8 TRTLLM review feedback

99178d6

Signed-off-by: seonjinn <sna@nvidia.com>

Clarify MXFP8 documentation wording

7d37af2

Signed-off-by: seonjinn <sna@nvidia.com>

Delete tests/kernels/quantization/test_mxfp8_trtllm_linear.py

eb2b0e0

Signed-off-by: Misha Goin <mgoin64@gmail.com>

mgoin approved these changes Aug 19, 2026

View reviewed changes

github-project-automation Bot moved this to Ready in NVIDIA Aug 19, 2026

mgoin added the ready ONLY add when PR is ready to merge/full CI is needed label Aug 19, 2026

Merge upstream main into feature/mxfp8-trtllm-linear-main

ec89789

Signed-off-by: seonjinn <sna@nvidia.com>

mgoin merged commit bd8865a into vllm-project:main Aug 20, 2026
94 of 95 checks passed

github-project-automation Bot moved this from Ready to Done in NVIDIA Aug 20, 2026

randomvariable mentioned this pull request Aug 21, 2026

Track upstream #52775 SM120 blockwise FP8 dispatch: stop routing misaligned-M GEMMs to swapAB — fork carries pre-fix gate randomvariable/vllm#56

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