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Summary
ROCm GPTQ/AWQ WNA16 MoE currently always calls
moe_align_block_size, evenwhen a very small decode batch activates only a sparse fraction of the expert
pool. vLLM's unquantized Triton MoE path already avoids that overhead with a
naive assignment mode in this regime.
This PR:
fused_moe_kernel_gptq_awq;aligned path; and
In naive mode, each program handles one routed token/expert pair. Lane zero is
valid and the remaining
BLOCK_SIZE_M - 1lanes are masked. The change ismodel-agnostic: it does not dispatch on model name, hidden size, expert count,
or other Ling-specific geometry.
Performance evidence
A fresh matched current-main A/B on AMD Radeon 8060S / Strix Halo (
gfx1151)compared upstream
75231eff2with this PR'sdf4c60d38. Three 32-token decoderows per side improved median throughput from 9.212774 to 10.363958 tok/s
(+12.50%). Response text and usage were identical across all six rows.
The CPU-isolation gates were 92.026% and 92.029% idle, respectively.
Both servers used
VLLM_ROCM_USE_SKINNY_GEMM=0to prevent the separate knowngfx1151 skinny-GEMM issue from obscuring this assignment-only comparison. JIT
warnings ended before either measured interval; no post-warmup JIT/autotuning,
preemption, HSA fault, device fault, or engine fault was observed.
The base and candidate intervals ran from 15:54:39.381–15:54:50.521 and
15:56:39.219–15:56:49.120 EDT, respectively, on August 8, 2026. They do not
overlap the documented August 7 host-contamination window.
Earlier matched Ling 3.0 Flash INT4/BF16 evidence changed only the assignment
route and improved median TG32 from 13.841172 to 17.000919 tok/s (+22.83%).
Seeded packed-INT4 W1/W2 fixtures were bitwise identical for unique and
duplicate expert IDs. The historical control has one retained row versus four
candidate rows, so the fresh current-main +12.50% result above is the primary
performance claim. A later 19.713926 tok/s result also included a separate
finalize-reduction change and is intentionally excluded from this PR's gain.
Duplicate search
GitHub issue/PR searches on August 8, 2026 for
WNA16 naive block assignment,WNA16 small token MoE, andfused_moe_kernel_gptq_awq alignmentfound nodirect duplicate. Adjacent work includes the merged generic unquantized naive
assignment PR #29354, the gfx1100-only native HIP W4A16 PR #44075, and CUDA
small-batch alignment PR #44167. None enables this ROCm Triton WNA16 route.
Tests
Current-main base:
75231eff2f3873e2bce7cc9558bb5227ea70b808.AMD Radeon 8060S / Strix Halo (
gfx1151), ROCm 7.15, Triton 3.8:The aggregate pre-commit command could not bootstrap its unrelated
Markdown/Node environment because the host Python CA chain rejected the Node
download. Every hook applicable to the changed Python files was run
individually and passed; certificate verification was not disabled.
Model evaluation
The patch changes assignment mechanics, not routing decisions, weights, or
numerics. Focused INT4, INT8, zero-point, and aligned-fallback GPU tests match
the existing reference path, and the retained full-model A/B produced
identical outputs.
AI assistance
AI-assisted. The human submitter reviewed and understands every changed line.
CIRU is the sole author, committer, and DCO signatory.
PR readiness checklist
gfx1151GPU tests completed.