[CPU] Restore linear dispatch for small unquantized GEMMs - #51379
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PR vllm-project#50801 removed the SGLang AMX weight_packed_linear path from the unquantized (bf16/fp16) linear dispatch, leaving oneDNN's onednn_mm as the only CPU kernel. For small weights -- most notably MoE router/gate projections, where N is the expert count rather than a hidden-size-scaled dimension -- oneDNN never reaches its compute-bound regime no matter how large the batch gets, so SGL's lower per-call dispatch overhead wins across the full measured M range. Restore that dispatch, gated by a weight-size threshold so larger dense projections (qkv/o_proj/gate_up/ down/lm_head) keep using oneDNN once batch size grows past decode-sized M. Also add a runtime AMX-FP16 capability check: AMX-BF16/INT8 (amx_tile) and AMX-FP16 are separate CPU ISA extensions (e.g. Sapphire/Emerald Rapids expose the former but not the latter), and SGL's can_use_brgemm<at::Half> always attempts brgemm for fp16 regardless of M, so fp16 needs its own capability gate rather than piggybacking on amx_tile. Signed-off-by: jiang1.li <jiang1.li@intel.com>
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jikunshang
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Purpose
PR #50801 removed the SGLang AMX
weight_packed_linearpath from the CPUunquantized (bf16/fp16) linear dispatch, leaving oneDNN's
onednn_mmas theonly kernel for that path. For small weights -- most notably MoE router/gate
projections, where N is the expert count rather than a hidden-size-scaled
dimension -- oneDNN never reaches its compute-bound regime regardless of
batch size, so the SGL kernel's lower per-call dispatch overhead wins across
the full measured M range. This restores that dispatch for weights small
enough to benefit, while leaving larger dense projections (qkv/o_proj/
gate_up/down/lm_head) on oneDNN.
Changes
check_cpu_sgl_kernel: restore dispatch to the SGL AMX kernel for bf16/fp16unquantized GEMMs, gated by a
_CPU_SGL_GEMM_MAX_WEIGHT_BYTES(1 MiB)weight-size threshold so it only applies to small weights (comfortably
covers MoE router/gate weights while staying below dense projections).
This threshold does not affect the existing int8 scaled_mm path, which is
a separate consumer of the same function.
torch.cpu._is_amx_fp16_supported)for the fp16 branch. AMX-BF16/INT8 (
amx_tile) and AMX-FP16 are separateCPU ISA extensions -- e.g. Sapphire/Emerald Rapids expose the former but
not the latter -- and SGL's
can_use_brgemm<at::Half>always attemptsbrgemm for fp16 regardless of M, so fp16 needs its own capability gate
rather than piggybacking on
amx_tile.Test Plan
Correctness (offline inference, dispatch path confirmed via debug logs):
End-to-end serving benchmark on the one locally-cached model with a genuinely
unquantized (fp16) router gate,
Qwen/Qwen3-30B-A3B-GPTQ-Int4:Test Result
Correctness: all three models produced coherent generations, with debug logs
confirming the expected dispatch on each linear:
above the 1 MiB threshold), unchanged from before this PR.
route to the SGL kernel, remaining dense linears to oneDNN -- both paths
exercised in one model.
to the SGL kernel, dense linears to oneDNN.
Kernel-level microbenchmarks (oneDNN vs SGL, geomean over 5 trials x 20 iters)
for router/gate-shaped GEMMs across the M range confirm SGL wins throughout,
e.g. for a (K=1536, N=64) bf16 gate shape (granite-4.0-h-tiny):
(values < 1 favor SGL; consistent with the existing kernel benchmark sweep
data for other router/gate shapes, e.g. Qwen3-30B-A3B's (K=2048, N=128) and
gpt-oss-20b's (K=2880, N=32).)