[ROCm][Perf] gfx942: use FlyDSL fp8 MQA logits kernel (ROCm/aiter#3913) - #49544
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Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
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@akii96 which aiter version is this validated on?? |
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As far as I know, I checked that our upstream v0.1.16.post5 aiter version does not contain the PR that you mentioned. So I will put this onhold. |
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I validated this on the nightly image from last Wednesday I believe and only cherry picked one vLLM PR #48886 which has the fix for the metadata issue. The release notes are a bit of one thing pointing to another but maybe this helps: The release notes of AITER v0.1.16.post5 mention it being on top of So if we were to look at release notes of this AITER v0.1.16.post4 It mentions the aiter PR 3913
Thanks for looking into this! Hope this clears up the confusion about the release notes @tjtanaa |
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Hi @tjtanaa vLLM’s current docker/Dockerfile.rocm_base now pins AITER v0.1.19, and the FlyDSL FP8 MQA logits kernel used by this PR is present here -> https://github.com/ROCm/aiter/blob/v0.1.19/aiter/ops/flydsl/kernels/fp8_mqa_logits.py I have not validated recently so if you need me to repeat against latest nightly happy to do so, just let me know! 😸 |
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@tjtanaa validated the perf benefits of this PR on DSv4 Flash (averaged over 2 runs of baseline trition and flydsl arms). Can you please review this again now and see if we can get this merged ? Also benefits DSv4 Pro (not measured here) which got a weight refresh today! Image: Serving commandexport HIP_VISIBLE_DEVICES=0,1,2,3,4,5,6,7
export VLLM_ROCM_USE_AITER=1
vllm serve deepseek-ai/DeepSeek-V4-Flash \
--trust-remote-code \
--kv-cache-dtype fp8 \
--block-size 256 \
--enable-expert-parallel \
--tensor-parallel-size 8 \
--distributed-executor-backend mp \
--gpu-memory-utilization 0.9 \
--max-num-seqs 512 \
--max-num-batched-tokens 8192 \
--compilation-config '{"mode": 3, "cudagraph_mode": "FULL_DECODE_ONLY"}' \
--tokenizer-mode deepseek_v4 \
--tool-call-parser deepseek_v4 \
--enable-auto-tool-choice \
--no-enable-prefix-caching \
--port 8000Performance
The change is performance-neutral at 8K and provides increasing perf boost at larger ISL GSM8K accuracy
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tjtanaa
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LGTM. Thanks for the evaluation and benchmark data.
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/ci run |
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✅ @akii96, CI is now available for this PR.
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✅ Triggered Buildkite CI #84091 for commit |
… (vllm-project#49544) Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
… (vllm-project#49544) Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com> Signed-off-by: Wyett <wyettzeng@gmail.com>
… (vllm-project#49544) Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com> Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
… (vllm-project#49544) Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com> Signed-off-by: khushali9 <khushali.desai9@gmail.com>

On gfx942, replace the vendored Triton
fp8_mqa_logitswithaiter.ops.flydsl.flydsl_fp8_mqa_logitsfrom ROCm/aiter#3913. Drop-in replacement (identical args/semantics), gated behind_ON_GFX942.gfx950 and other paths are untouched.
Results: GLM-5.2-FP8, 8× MI325X TP8
ISL=128K, OSL=1K, Conc=8
ISL=8K, OSL=1K, Conc=8
No regression at short context; gains scale with input length as seen above
Accuracy
Serve command
Bench command