[Attention][DSA] Route SM100 sparse-indexer decode through varlen paged MQA logits

[zyongye]

Purpose

On SM100 (Blackwell datacenter), route all DeepSeek sparse-attention indexer
decode through the DeepGEMM varlen paged MQA logits kernel, selected by
passing a per-row indices run-id to get_paged_mqa_logits_metadata /
fp8_fp4_paged_mqa_logits.

Today, variable-length decode on SM100 (spec/MTP with non-uniform accepted
lengths) hits the native multi-atom path, which pads to (B, max_decode_len)
and masks — wasted compute. The varlen path flattens decode into per-token rows
(next_n == 1) with an adjacency-grouped request id, so the kernel does no
padded work. Plain next_n==1 and uniform spec decode are unified onto the same
path (cheap: plain decode needs no expansion, just indices = arange(B)).

Changes

• vllm/utils/deep_gemm.py: optional indices kwarg on
  get_paged_mqa_logits_metadata and fp8_fp4_paged_mqa_logits, forwarded to
  the DeepGEMM impl only when set, so every existing non-varlen caller is
  byte-identical.
• vllm/v1/attention/backends/mla/indexer.py: add use_varlen
  (cuda + sm_10x + DeepGEMM); relax require_uniform / use_native so
  variable-length decode stays a decode instead of being split to prefill; build
  per-row indices (arange for plain, i // max_decode_len for uniform —
  static/cudagraph-safe, repeat_interleave for the eager variable case) into a
  preallocated buffer; new DecodeMetadata.indices field.
• vllm/model_executor/layers/sparse_attn_indexer.py: thread indices into
  the decode kernel call (FP8 and FP4 caches).

Off-SM100 (native / flatten) and XPU/ROCm paths are unchanged (use_varlen is
False there, indices stays None). storage_block_size is 64 for V3.2 and
block_size // compress_ratio = 64 for V4, satisfying the kernel's
block_kv ∈ {32, 64} constraint.

Not duplicating existing work

Searched open PRs (varlen indexer, paged mqa logits, sparse attn indexer,
indexer varlen decode). The nearest are different backends/areas:

• [ROCm][Perf] Enabled FP4Indexer for DSV4 #42908 (ROCm FP4 indexer for DSV4), [ROCm] Add per-call decode budget to sparse-MLA indexer #43327 (ROCm per-decode budget),
  [ROCm][DSv3.2] Eliminate per-decode FillFunctor launches in sparse-MLA hot loop #44527 (ROCm FillFunctor) — ROCm/AITER, not the SM100 DeepGEMM varlen path.
• [Attention][DSA][DCP] Support DCP for DeepSeek Sparse Attention #46178 / [Attention][MLA] FlashMLA sparse: enable DCP on the fp8 mixed-batch path and MTP with full cudagraphs #45426 / [Attention] Overlap sparse MLA indexer on a native CUDA side stream #47355 (DSA DCP work) — DCP scheduling, orthogonal.

None implement the SM100 varlen paged-MQA-logits indices decode path.

Testing

GSM8K with uniform decode and MTP passed.

Note

This change was written with AI assistance (Claude). It has not yet been
runtime-tested end-to-end; opening as a draft to track the verification above.

[claude]

Claude Code Review

This pull request is from a fork — automated review is disabled. A repository maintainer can comment @claude review to run a one-time review.

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @zyongye.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

[LucasWilkinson]

LGTM thanks for doing this!