[DSV4][XPU] Pass gemm1_clamp_limit to XpuFusedMoe#44517
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Add XPU-specific decode implementation for DeepSeek-V4 MLA sparse attention. Signed-off-by: Ma Jian <jian1.ma@intel.com>
- Add forward_xpu to MHCFusedPostPreOp (decomposes into mhc_post_torch + mhc_pre_torch) - Update XPU model forward to use fused MHC path (matching AMD pattern): first layer uses standalone hc_pre, middle layers use mhc_fused_post_pre - Add explicit hc_post after decoder loop Signed-off-by: Ma Jian <jian1.ma@intel.com>
Signed-off-by: Ma Jian <jian1.ma@intel.com>
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Summary
Pass
quant_config.gemm1_clamp_limittoXpuFusedMoeso that the SwiGLU clamp limit is applied during MoE expert computation on XPU.Dependencies
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