[Perf][ROCm] MoE int4 weight repacking for GPTQ/AWQ Triton kernel by amd-xavierwang · Pull Request #43389 · vllm-project/vllm

amd-xavierwang · 2026-05-22T03:59:25Z

[Perf][ROCm] MoE int4 interleave unpacking for GPTQ/AWQ Triton kernel

Optimizes the MoE int4 Triton kernel (fused_moe_kernel_gptq_awq) on ROCm by changing the memory packing scheme, mainly benefiting FP16 models.

The current kernel loads each packed int4 byte twice (once per nibble) and uses per-element variable shifts. This PR repacks weights at load time from K-packed [E, N, K//2] uint8 to N-packed [E, K, N//8] int32, then unpacks in-kernel via 3× tl.interleave with constant GPTQ sequential shifts. Zero points are also unpacked to fp16 during load time to avoid on-the-flay unpacking.

The goal of this GPTQ-style packed memory is to achieve overall better performance with an unified Triton kernel for Prefill + Decode. More compute-intensive Prefill benefit better from Exllama way of packing(refer to hybrid W4A16, and optimal skinny decode needs native HIP kernel. Leaving these to future work.

Inspiration:

The dense triton_w4a16.py kernel (upstream)
Matthias Gehre's hybrid W4A16 work

ROCm only. CUDA path is unchanged — interleave activates when use_int4_w4a16 and B.dtype == torch.int32, which only occurs after ROCm-gated weight repacking. The core idea technically extends to CUDA as well — but the CUDA kernel expects uint8 packed weights as input, so guarding this to prevent impacting CUDA paths.

What changes

MoeWNA16Method.process_weights_after_loading() (vllm/model_executor/layers/quantization/moe_wna16.py): On ROCm + int4, repacks weights from K-packed uint8 to N-packed int32, transposes scales, and repacks zero points (if asymmetric).
CompressedTensorsWNA16MoEMethod.process_weights_after_loading(): Same repacking for compressed-tensors models.
fused_moe_kernel_gptq_awq (vllm/model_executor/layers/fused_moe/fused_moe.py): New use_int4_interleave constexpr path. When B.dtype == torch.int32 (repacked weights detected), uses `tl.interleave to unpack at register level. Supports both symmetric and asymmetric quantization.
moe_problem_size override: Corrects the N dimension for the repacked layout.

Why fp16 is hit hardest on gfx1100

The dequantization path does int4 → f32 (dequant) → fp16/bf16 (truncate) → WMMA. Inspecting LLIR and AMDGCN reveals a type conversion cost asymmetry:

bf16→f32: trivial bit-shift (same 8-bit exponent range). LLVM lowers fptrunc float→bfloat to integer v_lshrrev/v_lshlrev ops. The WMMA intrinsic accepts <16 x i16> for bf16, so no float conversion pipeline is needed. 0 fptrunc/fpext instructions in the LLIR.
fp16→f32: real conversion (5-bit vs 8-bit exponent, needs rounding). LLVM emits v_cvt_f16_f32/v_cvt_f32_f16, each keeping both f32 source and fp16 result live simultaneously. 265 fptrunc/fpext instructions (136 trunc + 129 ext) inflate register pressure past the 256 VGPR budget.

The interleave path avoids this entirely by reducing the number of intermediate values in the inner loop regardless of dtype.

VGPR example analysis (`fused_moe_kernel_gptq_awq`, gfx1100)

Variant	VGPRs	VGPR Spills	Scratch (B)	Occupancy
PR fp16	144	0	0	10
PR bf16	163	0	0	9
Original fp16	256	219	880	5
Original bf16	256	133	416	5

Interleave eliminates all register spilling and doubles occupancy on gfx1100.

Benchmark results

AWQ: Qwen3-30B-A3B-AWQ (batched serve, ShareGPT 500 prompts)

fp16 → fp16 (AWQ default):

Metric	gfx1100 Main	gfx1100 PR	gfx1100 Δ	gfx1201 Main	gfx1201 PR	gfx1201 Δ
Output tok/s	392	957	+144%	685	928	+35%
Median TPOT (ms)	439	159	−64%	233	164	−30%
Median ITL (ms)	381	127	−67%	199	139	−30%
Median TTFT (ms)	29,166	19,259	−34%	21,263	18,093	−15%

bf16 → bf16 (--dtype bfloat16):

Metric	gfx1100 Main	gfx1100 PR	gfx1100 Δ	gfx1201 Main	gfx1201 PR	gfx1201 Δ
Output tok/s	863	897	+4%	875	892	+2%
Median TPOT (ms)	181	166	−8%	172	167	−3%
Median ITL (ms)	147	134	−9%	145	141	−3%
Median TTFT (ms)	13,875	20,388	+47%	17,861	17,713	−1%

The fp16 improvement (+144% on gfx1100, +35% on gfx1201) comes from eliminating VGPR spilling. The bf16 improvement (+2–4%) is the pure algorithmic gain. The gfx1100 bf16 TTFT regression is not observed on gfx1201. This compute-bound regression will be solved by the optimized Exllama packing Triton kernel in the future.

AWQ: Qwen3-30B-A3B-AWQ (single-batch decode, `max_num_seqs=1`, 100 prompts)

fp16 → fp16:

Metric	Main	this PR	Delta
Output tok/s	40.19	54.22	+35%
Median TPOT (ms)	24.14	17.95	−26%

bf16 → bf16:

Metric	Main	this PR	Delta
Output tok/s	50.15	51.64	+3%
Median TPOT (ms)	19.31	18.82	−3%

Compressed-Tensors: RedHatAI/Qwen3-30B-A3B-quantized.w4a16 (bf16 → bf16, batched serve, 500 prompts, warm avg)

Metric	Main	this PR	Delta
Output tok/s	1095	1245	+14%
Median TPOT (ms)	139.0	130.9	−6%
Median ITL (ms)	128.4	121.3	−6%
Median TTFT (ms)	1635	1598	−2%

GPTQ: Qwen3.5-35B-A3B-GPTQ-Int4 (fp16 → fp16, 256 experts, batched serve, 500 prompts, warm avg)

Metric	Main	this PR	Delta
Output tok/s	517	556	+7%
Total tok/s	1013	1097	+8%
Median TTFT (ms)	20,073	18,624	−7%
Median ITL (ms)	189	179	−5%

Accuracy (lm_eval gsm8k, 5-shot, 200 samples, gfx1100)

Model	Branch	strict-match	flexible-extract
Qwen3-30B-A3B-AWQ	main	0.920 ± 0.019	0.890 ± 0.022
Qwen3-30B-A3B-AWQ	PR	0.915 ± 0.020	0.885 ± 0.023
RedHatAI/Qwen3-30B-A3B-quantized.w4a16	main	0.900 ± 0.021	0.910 ± 0.020
RedHatAI/Qwen3-30B-A3B-quantized.w4a16	PR	0.895 ± 0.022	0.890 ± 0.022

No accuracy regression — all deltas are within stderr.

Test plan

lm_eval gsm8k 5-shot accuracy (AWQ + CompressedTensors)
End-to-end serving benchmark (AWQ fp16/bf16, CT bf16, GPTQ fp16)
Single-batch decode latency (AWQ fp16/bf16)
VGPR spilling analysis (.amdgcn dump inspection)

github-actions · 2026-05-22T03:59:34Z

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mergify · 2026-05-22T04:00:04Z

Documentation preview: https://vllm--43389.org.readthedocs.build/en/43389/

gemini-code-assist

Code Review

This pull request introduces an N-packed "interleave" weight layout for MoE int4 quantization on ROCm, aimed at optimizing the Triton kernel by reducing memory bandwidth and ALU overhead. The implementation includes a repacking mechanism during weight loading, updates to the fused_moe kernel to utilize tl.interleave for efficient unpacking, and extensive benchmarking documentation. Feedback identifies a critical missing boundary check for packed indices that could cause out-of-bounds memory access and suggests validating that BLOCK_SIZE_N is a multiple of 8 to prevent shape mismatches during broadcasting.

AndreasKaratzas

So the first thing that I see is that there is a definitive .5% acc decrement, that it is OK if there is such a perf bump, but it should probably be optional. I'll also let @dllehr-amd and @tjtanaa comment on this. Also there must definitely be an evaluation on other archs and models. But those are my initial thoughts on this PR.

amd-xavierwang · 2026-05-28T01:56:42Z

So the first thing that I see is that there is a definitive .5% acc decrement, that it is OK if there is such a perf bump, but it should probably be optional. I'll also let @dllehr-amd and @tjtanaa comment on this. Also there must definitely be an evaluation on other archs and models. But those are my initial thoughts on this PR.

Thank you so much for the feedback! I am new to vLLM and I am grateful to receive various feedbacks from reviewers. Most MOE models are having a hard time to fit on single gfx11/12 other than the Qwen family. I will try if Mixtral-8x7B-Instruct-v0.1 works.

Meanwhile, the acc was only ran for 1 base model asym + sym. I will try on other models to validate.

dllehr-amd · 2026-05-28T02:40:21Z

okay a few things here first.

This looks like it's interleaving for all int4 moe's not just the gfx11/gfx12. This can be dangerous without looking through the gfx9 series for instinct lines. Have you tested this on any other arch's to ensure this doesn't cause regression, or worse accuracy/compatibility failures?

Also can you list the vllm launch commands you used and the ISL/OSL/Concurrency that was involved? These are critical to know the robustness of the tests and if we need to repro anything.

tjtanaa · 2026-05-28T09:12:49Z

So the first thing that I see is that there is a definitive .5% acc decrement, that it is OK if there is such a perf bump, but it should probably be optional. I'll also let @dllehr-amd and @tjtanaa comment on this. Also there must definitely be an evaluation on other archs and models. But those are my initial thoughts on this PR.

Yes agree with that, this feature should be optional as the degradation in acc is significant.

Another thing, @amd-xavierwang always run the full evaluation dataset, you are only using 200 samples, the variance can be high. Please share your lmeval accuracy score again once you rerun with full dataset.

tjtanaa · 2026-05-28T09:15:32Z

@bnellnm could you take a look as well. It is also modifying a common path.

bnellnm · 2026-06-01T20:17:01Z

@@ -514,7 +439,10 @@ def apply(
        apply_router_weight_on_input: bool,
    ):
        # Check constraints.
-        if self.quant_config.use_int4_w4a16:
+        _interleave = self.quant_config.use_int4_w4a16 and w1.dtype == torch.int32


Can you make the interleave check a method on FusedMoEQuantConfig? e.g. is_int4_w4a16_interleaved()?

bnellnm · 2026-06-01T20:18:16Z

-        )
-        b_shifter = (offs_k[:, None] % 2) * 4
+        if use_int4_interleave:
+            # B: [E, K, N//8] int32 — N-packed, 8 int4 per int32


Should we assert that N % 8 == 0 (and or BLOCK_SIZE_N) here?

Should we assert that N % 8 == 0 (and or BLOCK_SIZE_N) here?

should we keep assertion inside Triton kernel/hoist to launching?

bnellnm · 2026-06-01T20:28:37Z

+    Output: N-packed int32 (8 int4 per int32, GPTQ sequential shifts
+            [0,4,...,28]).
+    """
+    E, N, K_half = w.shape


Should this function also assert that N % 8 == 0?

amd-xavierwang · 2026-06-03T19:05:16Z

Further accuracy investigation on gfx1100, gfx1201 and gfx1151:

Used lm_eval, FULL dataset:

Command used:

lm_eval --model vllm \
  --model_args "pretrained=<model>,trust_remote_code=true,max_model_len=4096" \
  --tasks gsm8k --num_fewshot 5 --batch_size auto --seed 0,1234,1234,1234

single seed gfx12 runs

Model	Dtype	metric	main	PR	Δ (pp)
Qwen3-30B-A3B-AWQ	fp16	strict	0.8863 ±0.0087	0.8855 ±0.0088	−0.08
Qwen3-30B-A3B-AWQ	fp16	flex	0.8620 ±0.0095	0.8658 ±0.0094	+0.38
Qwen3-30B-A3B-AWQ	bf16	strict	0.8817 ±0.0089	0.8810 ±0.0089	−0.07
Qwen3-30B-A3B-AWQ	bf16	flex	0.8597 ±0.0096	0.8605 ±0.0095	+0.08
Qwen3-30B-A3B-w4a16	fp16	strict	0.8825 ±0.0089	0.8848 ±0.0088	+0.23
Qwen3-30B-A3B-w4a16	fp16	flex	0.8688 ±0.0093	0.8749 ±0.0091	+0.61
Qwen3-30B-A3B-w4a16	bf16	strict	0.8802 ±0.0089	0.8886 ±0.0087	+0.84
Qwen3-30B-A3B-w4a16	bf16	flex	0.8848 ±0.0088	0.8901 ±0.0086	+0.53
gemma-4-26B-A4B-it-AWQ-4bit	bf16	strict	0.4026 ±0.0135	0.4071 ±0.0135	+0.45
gemma-4-26B-A4B-it-AWQ-4bit	bf16	flex	0.4018 ±0.0135	0.4155 ±0.0136	+1.37

single seed gfx1151 runs

Model	Dtype	metric	main	PR	Δ (pp)
Qwen3-30B-A3B-AWQ	fp16	strict	0.8848 ±0.0088	0.8886 ±0.0087	+0.38
Qwen3-30B-A3B-AWQ	fp16	flex	0.8605 ±0.0095	0.8688 ±0.0093	+0.83
Qwen3-30B-A3B-AWQ	bf16	strict	0.8840 ±0.0088	0.8870 ±0.0087	+0.30
Qwen3-30B-A3B-AWQ	bf16	flex	0.8666 ±0.0094	0.8597 ±0.0096	−0.69
Qwen3-30B-A3B-w4a16	fp16	strict	0.8863 ±0.0087	0.8886 ±0.0087	+0.23
Qwen3-30B-A3B-w4a16	fp16	flex	0.8772 ±0.0090	0.8779 ±0.0090	+0.07
Qwen3-30B-A3B-w4a16	bf16	strict	0.8870 ±0.0087	0.8893 ±0.0086	+0.23
Qwen3-30B-A3B-w4a16	bf16	flex	0.8840 ±0.0088	0.8825 ±0.0089	−0.15
gemma-4-26B-A4B-it-AWQ-4bit	bf16	strict	0.3844 ±0.0134	0.4162 ±0.0136	+3.18
gemma-4-26B-A4B-it-AWQ-4bit	bf16	flex	0.3973 ±0.0135	0.4193 ±0.0136	+2.20

Single-seed cross-arch summary table (% delta: PR - main)

Model	Dtype	Strict gfx1100(rerun)	Strict gfx1151	Strict gfx1201	Flex gfx1100(rerun)	Flex gfx1151	Flex gfx1201
Qwen3-30B-A3B-AWQ	fp16	+0.61	+0.38	-0.08	+0.53	+0.83	+0.38
Qwen3-30B-A3B-AWQ	bf16	-0.61	+0.30	-0.07	-0.53	-0.69	+0.08
Qwen3-30B-A3B-w4a16	fp16	-0.53	+0.23	+0.23	-0.15	+0.07	+0.61
Qwen3-30B-A3B-w4a16	bf16	-0.30	+0.23	+0.84	+0.30	-0.15	+0.53
gemma-4-26B-A4B-AWQ-4bit	bf16	-1.90	+0.45	+0.45	-2.28	+1.37	+2.20

Most deltas are well within 1-sigma SE (~0.9pp for Qwen, ~1.35pp for gemma). Gemma however has lower accuracy only on gfx1100.

Multi-seed validation (gfx1100, all models, 3 seeds)

Run	`--seed`
Seed 0	`0,1234,1234,1234`
Seed 1	`1,2345,2345,2345`
Seed 2	`2,3456,3456,3456`

Model	Dtype	Seed	main strict	PR strict	main flex	PR flex	Δstrict	Δflex
Qwen3-30B-A3B-AWQ	fp16	0	0.8825	0.8870	0.8582	0.8704	+0.45	+1.22
Qwen3-30B-A3B-AWQ	fp16	1	0.8969	0.8999	0.8832	0.8848	+0.30	+0.16
Qwen3-30B-A3B-AWQ	fp16	2	0.8901	0.8901	0.8635	0.8666	+0.00	+0.31
Qwen3-30B-A3B-AWQ	bf16	0	0.8848	0.8825	0.8673	0.8650	−0.23	−0.23
Qwen3-30B-A3B-AWQ	bf16	1	0.8908	0.8848	0.8696	0.8597	−0.60	−0.99
Qwen3-30B-A3B-AWQ	bf16	2	0.8772	0.8901	0.8544	0.8650	+1.29	+1.06
Qwen3-30B-A3B-w4a16	fp16	0	0.8810	0.8878	0.8741	0.8825	+0.68	+0.84
Qwen3-30B-A3B-w4a16	fp16	1	0.8893	0.8893	0.8848	0.8863	+0.00	+0.15
Qwen3-30B-A3B-w4a16	fp16	2	0.9022	0.9030	0.8923	0.8939	+0.08	+0.16
Qwen3-30B-A3B-w4a16	bf16	0	0.8863	0.8832	0.8863	0.8817	−0.31	−0.46
Qwen3-30B-A3B-w4a16	bf16	1	0.8916	0.8908	0.8878	0.8840	−0.08	−0.38
Qwen3-30B-A3B-w4a16	bf16	2	0.8931	0.8946	0.8886	0.8840	+0.15	−0.46
gemma-4-26B-A4B-AWQ-4bit	bf16	0	0.4086	0.4117	0.4177	0.4139	+0.31	−0.38
gemma-4-26B-A4B-AWQ-4bit	bf16	1	0.3958	0.4147	0.4041	0.4208	+1.89	+1.67
gemma-4-26B-A4B-AWQ-4bit	bf16	2	0.4056	0.4321	0.4109	0.4314	+2.65	+2.05

Mean delta per model x dtype (PR - main, pp):

Model	Dtype	Mean Δstrict	Mean Δflex	total # seeds
Qwen3-30B-A3B-AWQ	fp16	+0.25	+0.56	3
Qwen3-30B-A3B-AWQ	bf16	+0.15	-0.05	3
Qwen3-30B-A3B-w4a16	fp16	+0.25	+0.38	3
Qwen3-30B-A3B-w4a16	bf16	-0.08	-0.43	3
gemma-4-26B-A4B-AWQ-4bit	bf16	+1.62	+1.11	3
All cells		+0.44	+0.31	15

Conclusion

The 0.5% accuracy drop was likely real, but it's due to high variance not using the full dataset, and the drop doesn't generalize across all RDNA GPUs. Using different seeds can slightly affect accuracy as well.

amd-xavierwang · 2026-06-04T03:10:06Z

Other changes post accuracy analysis:

Address bnellnm comments and put more assertions.
Guarding this PR to RDNA - CDNA likely doesn't have register pressure. Our team only has access to MI308 so I can't validate on ALL types of MIs. For now, conservatively guard it. (All of gfx1100, gfx1151 and gfx1201 show no regression).
- **Potential concern: ongfx1x() in the future can't be used as guard for RDNA with CDNA4 coming in. Will track to update the guard function.

vLLM command used for performance benchmarking:

Server:
vllm serve <model> --max_model_len 4096 --gpu_memory_utilization 0.90

Benchmark:
vllm bench serve \
  --model <model> \
  --dataset-name sharegpt \
  --dataset-path <path>/ShareGPT_V3_unfiltered_cleaned_split.json \
  --num-prompts 500

The ShareGPT dataset has variable ISL/OSL, and no --max-concurrency was set. I can try fixed ISL/OSL if there is the need.

@dllehr-amd @AndreasKaratzas Appreciate further insights!!

AndreasKaratzas · 2026-06-04T21:49:31Z

I don't feel comfortable reviewing this PR. The conclusions and comments look like AI generated, and I don't currently have the time to sit down and test it myself.

amd-xavierwang · 2026-06-05T00:39:23Z

I don't feel comfortable reviewing this PR. The conclusions and comments look like AI generated, and I don't currently have the time to sit down and test it myself.

The conclusion was validated by 2 members on my team and obvious through the table.

For single seed, accuracy drop does occur for certain models, but only on single type of GPU and does not generalize across all of {gfx1100, gfx1151, gfx1201}.

For multi-seed, accuracy drop is observed for particular seed and does not appear for all 3 seeds. The conclusion is that acc drop doesn't generalize for all RDNAs, nor for all seeds.

I did use the agent to help me generating the 3 random seeds for benchmarking and the full command arguments to use lm_eval, as this is my first time using it. If vLLM has standard way of use lm_eval, please let me know.

amd-xavierwang · 2026-06-05T23:38:18Z

@bnellnm Due to your work #44570, should I wait till your change get merged? I think they conflict.

amd-xavierwang · 2026-06-06T04:24:49Z

rerun lm_eval with online server, FULL dataset

Referencing #43385's command, I used:

# Server
vllm serve /mnt/nas_share/models/Qwen/Qwen3.5-35B-A3B-GPTQ-Int4 \
  --gpu-memory-utilization 0.90 --max-model-len 16384 \
  --tensor-parallel-size 1 --port 8000

# lm_eval:
lm_eval --model local-completions \
  --model_args "model=<model_path>,base_url=http://localhost:8000/v1/completions,num_concurrent=32,max_retries=3,timeout=600" \
  --batch_size auto \
  --tasks gsm8k \
  --num_fewshot 5 \
  --output_path <log_path> \
  --log_samples

Results: 1 symmetric model + asymmetric model on gfx1100

Qwen3-30B-A3B-AWQ PR:
|Tasks|Version|     Filter     |n-shot|  Metric   |   |Value |   |Stderr|
|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|
|gsm8k|      3|flexible-extract|     5|exact_match|↑  |0.8597|±  |0.0096|
|     |       |strict-match    |     5|exact_match|↑  |0.8878|±  |0.0087|

Qwen3-30B-A3B-AWQ Main:
|Tasks|Version|     Filter     |n-shot|  Metric   |   |Value |   |Stderr|
|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|
|gsm8k|      3|flexible-extract|     5|exact_match|↑  |0.8635|±  |0.0095|
|     |       |strict-match    |     5|exact_match|↑  |0.8832|±  |0.0088|

Qwen3.5-35B-A3B-GPTQ-Int4 PR (trial 1):
|Tasks|Version|     Filter     |n-shot|  Metric   |   |Value |   |Stderr|
|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|
|gsm8k|      3|flexible-extract|     5|exact_match|↑  |0.6513|±  |0.0131|
|     |       |strict-match    |     5|exact_match|↑  |0.6179|±  |0.0134|

Qwen3.5-35B-A3B-GPTQ-Int4 Main (trial 1):
|Tasks|Version|     Filter     |n-shot|  Metric   |   |Value |   |Stderr|
|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|
|gsm8k|      3|flexible-extract|     5|exact_match|↑  |0.6626|±  |0.0130|
|     |       |strict-match    |     5|exact_match|↑  |0.6308|±  |0.0133|

Qwen3.5-35B-A3B-GPTQ-Int4 PR (trial 2):
|Tasks|Version|     Filter     |n-shot|  Metric   |   |Value |   |Stderr|
|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|
|gsm8k|      3|flexible-extract|     5|exact_match|↑  |0.6725|±  |0.0129|
|     |       |strict-match    |     5|exact_match|↑  |0.6384|±  |0.0132|

Qwen3.5-35B-A3B-GPTQ-Int4 Main (trial 2):
|Tasks|Version|     Filter     |n-shot|  Metric   |   |Value |   |Stderr|
|-----|------:|----------------|-----:|-----------|---|-----:|---|-----:|
|gsm8k|      3|flexible-extract|     5|exact_match|↑  |0.6391|±  |0.0132|
|     |       |strict-match    |     5|exact_match|↑  |0.6103|±  |0.0134|

It seems like fluctuations exist even for the full dataset. But non demonstrates the consistent 0.5% acc drop like the 200 samples. The verbose, offline evaluation is done above as reference.
@tjtanaa

tjtanaa · 2026-06-06T16:19:55Z

Due to your work #44570, should I wait till your change get merged? I think they conflict.

we will go for this #44570 first.

amd-xavierwang · 2026-06-07T00:43:16Z

Thank you for enabling CI!! I will wait to address all remaining problems:

Resolve conflict after [MoE Refactor] Combine CompressedTensorsWNA16MarlinMoEMethod with CompressedTensorsWNA16MoEMethod #44570 has been merged.
Address DCO authorship
Wait for rocm.py 's update for true RDNA guard, as MI450 will be one of "on_gfx1x()"

mergify · 2026-07-22T03:22:16Z

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @amd-xavierwang.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

…#43389 widened) amd-xavierwang's int4 MoE repacking, gated upstream to RDNA, widened to GFX9 after measuring it here. fused_moe_kernel_gptq_awq on 2x MI210, rocprofv3, median of 160 launches: M=1 1.81x M=8 4.80x M=32 1.45x M=128 3.60x Bit-identical output at every size, against an old-vs-old determinism control. Covers the compressed-tensors path; awq/gptq via moe_wna16.py is left for later. Signed-off-by: David <davetha@users.noreply.github.com>

… (RDNA) Repack int4 W4A16 MoE weights from K-packed uint8 [E,N,K//2] to N-packed int32 [E,K,N//8] so the GPTQ/AWQ Triton kernel unpacks them with tl.interleave instead of per-element shifts, cutting VGPR pressure on RDNA. The repack is centralized in the WNA16 oracle's TRITON branch (convert_to_wna16_moe_kernel_format), covering both the MoeWNA16 (AWQ/GPTQ) and compressed-tensors sources. It is guarded to AMD RDNA (gfx11/gfx12) and int4. w13 and w2 feed separate kernel launches and dispatch per-tensor on dtype, so each is repacked independently and only when its N % 8 == 0; otherwise that weight keeps the uint8 layout and the kernel falls back to scalar shifts. Zero points are unpacked to fp16 for the AWQ case (compressed-tensors MoE is symmetric). Adds is_int4_w4a16_interleaved() on FusedMoEQuantConfig for dtype-based dispatch. benchmark_moe.py mirrors the same per-weight repack for int4 on RDNA so tuning targets the interleaved kernel that actually runs. Signed-off-by: Xavier Wang <xawang@amd.com>

Reflow the RDNA repack comments in the WNA16 oracle and benchmark_moe; drop the zero-point note (the None guard is self-explanatory) and fix a typo. Signed-off-by: Xavier Wang <xawang@amd.com>

… pp2048) Adapted vllm-project/vllm#43389 (open, unmerged, AMD-authored) as a local patch for the flashnext image: repacks W4A16 MoE weights at load time from K-packed [E, N, K//2] uint8 to N-packed [E, K, N//8] int32, unpacked in-kernel via tl.interleave (fewer VGPRs than per-element variable shifts). Gated behind on_rdna() + num_bits==4; author validated no gsm8k accuracy regression on gfx1100/gfx1151/gfx1201 (our arch). Measured on qwen3.8-flash-next-aixiaoma (TP4, bf16 KV, MTP4, util 0.95): - pp2048: ~700-780 -> 2344-2346 t/s (~3x) - tg32/tg128: unchanged within run-to-run noise - coherence + multi-turn growing-prefix probe: PASS Tradeoff: model weight footprint unchanged (19.95 GiB/GPU), but the patched kernel's profiling forward pass uses ~3.5-4 GiB more peak activation memory, cutting the usable ctx ceiling @ util 0.95 from 262144 to ~158304. Cut VLLM_MAX_MODEL_LEN on qwen3.8-flash-next-aixiaoma.env from 262144 to 155000 to leave headroom. Documented in README (new 'Flash-Next source-build patches' section) and BENCHMARKS.md/benchmarks/2026-08-28_qwen3.8-flash-next_43389_moe_patch_bench.md. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

mergify Bot added documentation Improvements or additions to documentation performance Performance-related issues rocm Related to AMD ROCm labels May 22, 2026

github-project-automation Bot added this to AMD May 22, 2026

github-project-automation Bot moved this to Todo in AMD May 22, 2026

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Comment thread vllm/model_executor/layers/fused_moe/fused_moe.py Outdated

Comment thread vllm/model_executor/layers/fused_moe/fused_moe.py Outdated

amd-xavierwang force-pushed the moe-interleave-fp16-zeros branch 4 times, most recently from a4d2649 to 38d6f22 Compare May 25, 2026 18:03

amd-xavierwang changed the title ~~[Perf][ROCm] MoE int4 interleave unpacking for GPTQ/AWQ Triton kernel~~ [Perf][ROCm] MoE int4 weight repacking for GPTQ/AWQ Triton kernel May 27, 2026

amd-xavierwang force-pushed the moe-interleave-fp16-zeros branch from ceac06c to aed94af Compare May 27, 2026 20:24

amd-xavierwang marked this pull request as ready for review May 27, 2026 20:28

amd-xavierwang requested review from WoosukKwon, mgoin, pavanimajety, robertgshaw2-redhat, tlrmchlsmth, yewentao256 and zyongye as code owners May 27, 2026 20:28

AndreasKaratzas reviewed May 27, 2026

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tjtanaa requested a review from bnellnm May 28, 2026 09:15

bnellnm reviewed Jun 1, 2026

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bnellnm approved these changes Jun 3, 2026

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amd-xavierwang force-pushed the moe-interleave-fp16-zeros branch from 14c3255 to a88c90a Compare June 4, 2026 02:29

amd-xavierwang requested a review from AndreasKaratzas June 4, 2026 03:10

amd-xavierwang mentioned this pull request Jun 5, 2026

[ROCm][Perf] Fused MoE W4A16 HIP kernel for AMD RDNA3 (gfx1100) #44075

Merged

tjtanaa added the ready ONLY add when PR is ready to merge/full CI is needed label Jun 6, 2026

wjabbour mentioned this pull request Jun 15, 2026

[MoE Refactor] Combine CompressedTensorsWNA16MarlinMoEMethod with CompressedTensorsWNA16MoEMethod #44570

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lhl mentioned this pull request Jun 19, 2026

[ROCm] Enable RDNA3 W4A16 GEMM kernels on gfx1151 (Strix Halo) #46186

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afierka-intel mentioned this pull request Jul 7, 2026

[Kernel] Tensor-descriptor path for fused_moe_kernel_gptq_awq (int4) afierka-intel/vllm#6

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mergify Bot added needs-rebase quantization labels Jul 22, 2026

amd-xavierwang force-pushed the moe-interleave-fp16-zeros branch from 4da4ef3 to f5d8dc2 Compare August 4, 2026 19:17

mergify Bot removed the needs-rebase label Aug 4, 2026

[Perf][ROCm] Tidy int4 interleave repack comments

56ef89e

Reflow the RDNA repack comments in the WNA16 oracle and benchmark_moe; drop the zero-point note (the None guard is self-explanatory) and fix a typo. Signed-off-by: Xavier Wang <xawang@amd.com>

afierka-intel mentioned this pull request Aug 17, 2026

[Kernel][Quantization][XPU] Tensor-descriptor path for fused_moe_kernel_gptq_awq (int4) #52652

Open

JartX mentioned this pull request Sep 6, 2026

[Refactor][ROCm] Migrate the RDNA3 W4A16 MoE to the oracle/experts pa… #55522

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Rafa-Innerchispa mentioned this pull request Sep 14, 2026

docs: record R9700 upstream delta review Rafa-Innerchispa/hyperloom-r9700-experimental#8

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amd-xavierwang commented May 22, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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[Perf][ROCm] MoE int4 interleave unpacking for GPTQ/AWQ Triton kernel

What changes

Why fp16 is hit hardest on gfx1100

VGPR example analysis (fused_moe_kernel_gptq_awq, gfx1100)

Benchmark results

AWQ: Qwen3-30B-A3B-AWQ (batched serve, ShareGPT 500 prompts)

AWQ: Qwen3-30B-A3B-AWQ (single-batch decode, max_num_seqs=1, 100 prompts)

Compressed-Tensors: RedHatAI/Qwen3-30B-A3B-quantized.w4a16 (bf16 → bf16, batched serve, 500 prompts, warm avg)

GPTQ: Qwen3.5-35B-A3B-GPTQ-Int4 (fp16 → fp16, 256 experts, batched serve, 500 prompts, warm avg)

Accuracy (lm_eval gsm8k, 5-shot, 200 samples, gfx1100)

Test plan

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Code Review

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amd-xavierwang commented Jun 3, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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Further accuracy investigation on gfx1100, gfx1201 and gfx1151:

single seed gfx12 runs

single seed gfx1151 runs

Single-seed cross-arch summary table (% delta: PR - main)

Multi-seed validation (gfx1100, all models, 3 seeds)

Conclusion

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amd-xavierwang commented Jun 4, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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Other changes post accuracy analysis:

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AndreasKaratzas commented Jun 4, 2026

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amd-xavierwang commented Jun 5, 2026

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amd-xavierwang commented Jun 6, 2026

rerun lm_eval with online server, FULL dataset

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tjtanaa commented Jun 6, 2026

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amd-xavierwang commented May 22, 2026 •

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VGPR example analysis (`fused_moe_kernel_gptq_awq`, gfx1100)

AWQ: Qwen3-30B-A3B-AWQ (single-batch decode, `max_num_seqs=1`, 100 prompts)

amd-xavierwang commented May 28, 2026 •

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