[Kernel] Fuse Qwen2/3-MoE shared-expert sigmoid gate into a Triton kernel

[haofrank]

Purpose

Resolves #43187.

Qwen2MoeMLP.forward / Qwen3MoeMLP.forward currently apply the shared-expert gate as F.sigmoid(self.expert_gate(x)[0]) * out, which dispatches three separate GPU kernels with two [N, 1] HBM-resident intermediates (the linear logits and the sigmoid of those logits). Because the gate weight is ReplicatedLinear(hidden_size, 1), the "matmul" is really a per-row dot product, so the trip through cuBLAS / hipBLAS is pure overhead on top of the avoidable extra reads/writes.

This PR introduces fused_shared_expert_gate, a row-fused Triton kernel under vllm/model_executor/layers/fused_moe/shared_expert_gate.py, that loads x, the gate weight, and out once per row and stores the final result. Both qwen2_moe.py and qwen3_moe.py swap their three-kernel tail for a single call into this helper.

The wrapper is shape-guarded and silently falls back to the PyTorch reference (F.sigmoid(F.linear(x, weight)) * out) for any input shape this kernel does not handle, so it is safe to use unconditionally behind the existing expert_gate call sites.

Relationship to existing FSE work

Complementary to #39280 (AITER FSE), not overlapping. FSE (VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS, default False) bypasses the call site at the MoE-block level on ROCm + AITER with explicit opt-in. For NVIDIA, ROCm with AITER off, ROCm + AITER + default, and all qwen3_moe.py configs (FSE PR did not touch the duplicate gate code), the slow 3-kernel path runs today. The wrapper here is a no-op when FSE is enabled — the two never execute simultaneously. See #43187 for the full discussion (also covers #37800, the open PR proposing to flip the FSE default on ROCm).

Test Plan

Inside a Triton-capable GPU container (CUDA or ROCm):

PYTHONPATH=/path/to/vllm pytest tests/kernels/moe/test_fused_shared_expert_gate.py -v

The new test parametrizes over real Qwen3-Next-style shapes (K ∈ {1024, 2048}, N ∈ {1, 7, 33, 1024, 7177, 8192}, dtype ∈ {bf16, fp16}) plus a 3D-input fallback case that exercises the shape-guard path.

Test Result

Correctness (25/25 passing)

Inside vllm/vllm-openai-rocm:nightly on MI355x (gfx950), GPU 0:

======================= 25 passed, 17 warnings in 10.66s =======================

End-to-end throughput

Single MI355x, Qwen3-Next-80B-A3B-Instruct-FP8, vLLM 0.19.1, TP=1, AITER on, FSE off. Output throughput Δ (fused vs baseline) across three workload shapes × three concurrencies:

Workload	CONC=16	CONC=32	CONC=64	mean
balanced (ISL=OSL=1024)	+2.69%	+7.09%	+4.18%	+4.65%
decode-heavy (ISL=1024 / OSL=8192)	+5.99%	+6.96%	+6.12%	+6.36%
prefill-heavy (ISL=8192 / OSL=1024)	+3.87%	+12.68%	+14.32%	+10.29%

Kernel-only microbench (bf16, MI355x) shows 1.22–1.36× on real Qwen3-Next shapes (N ∈ {1024, 7177, 8192}, K=2048). Detailed Pareto plots and per-cell numbers in a benchmark HTML available on request — happy to attach if reviewers want them.

I will re-run on main HEAD once direction is approved; the call sites at the v0.19.1 commit and current main HEAD are unchanged, so the numbers should carry over.

---

AI assistance disclosure (per AGENTS.md §1)

This PR was prepared with AI assistance (Cursor + Claude). The submitting human (@haofrank) reviewed every changed line, designed the test matrix, ran pytest + bench on MI355x, and is responsible for the contribution end-to-end. See the Co-authored-by: Claude and Co-authored-by: Cursor trailers on the commit.

cc @sighingnow @vadiklyutiy (qwen models codeowners), @mgoin @pavanimajety @zyongye (fused_moe codeowners), @tlrmchlsmth @WoosukKwon @yewentao256 (tests/kernels codeowners), @tpopp @dllehr-amd (FSE authors), @ChuanLi1101 (#37800 author).

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[gemini-code-assist]

Code Review

This pull request introduces a fused Triton kernel for the Qwen2/3-MoE shared-expert sigmoid gate, replacing the three-kernel PyTorch reference to reduce memory overhead. Review feedback highlights a critical need to handle non-contiguous tensors by incorporating row strides into the kernel and wrapper, as well as adding test cases to verify correctness for sliced or non-standard stride inputs.

[haofrank]

Thanks for the thorough review @gemini-code-assist! All three comments addressed in 67de337:

1. Kernel — accept row strides (shared_expert_gate.py): kernel now takes stride_x_n / stride_out_n / stride_y_n and indexes rows by the actual stride instead of row * K. Same Triton instruction count, same perf on the contiguous fast path (strides are constant-folded), but no more silent corruption on views.

2. Wrapper — guard non-unit inner stride + pass strides: fallback guard now also rejects x.stride(1) != 1, out.stride(1) != 1, weight.stride(1) != 1; output is now allocated explicitly contiguous via torch.empty_like(out, memory_format=torch.contiguous_format).

3. Tests — sliced inputs: added two new tests:

   • test_fused_shared_expert_gate_handles_sliced_row_stride — x[:, :K] over a [N, 2K] buffer (row stride 2K, inner stride 1) → exercises the kernel path with non-trivial row stride.
   • test_fused_shared_expert_gate_falls_back_on_non_unit_inner_stride — x[:, ::2] (inner stride 2) → asserts the fallback path is taken and matches the PyTorch reference.

Local result inside vllm/vllm-openai-rocm:nightly on MI300X&MI355X: 27/27 passing.

[gemini-code-assist]

Thanks for the update, @haofrank. The changes to shared_expert_gate.py and the added regression tests look great. Addressing the row stride and inner stride handling ensures the kernel is robust for various input configurations. The test coverage for sliced inputs and fallback paths is appreciated. This looks ready for further CI validation.

[rbrugaro-amd]

@haofrank What is the throughput comparison when VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS=1 (FSE on)? FSE fuses the entire shared expert into the routed MoE kernel, which should be a strictly larger optimization. How does the FSE-on throughput compare to this PR's approach?

[haofrank]

Thanks @rbrugaro-amd! they don't overlap. When FSE=1 fires the standalone shared expert isn't instantiated and our path is unreachable; agreed it's strictly larger where it applies.

Two reasons to land this:

1. FSE is ROCm + gfx9 + AITER only (the @if_aiter_supported decorator on is_fusion_moe_shared_experts_enabled). NVIDIA users, ROCm users without AITER, and ROCm on non-gfx9 archs all fall through to the 3-kernel tail today, this PR is the only optimization those configs get on Qwen2/3-MoE.

2. Even on the targeted ROCm+AITER path, FSE isn't wired through qwen2_moe.py / qwen3_moe.py — Qwen2MoeSparseMoeBlock / Qwen3MoeSparseMoeBlock never check is_fusion_moe_shared_experts_enabled() — so the 3-kernel tail still runs on Qwen3-30B-A3B / 235B-A22B / Coder-480B-A35B and Qwen2-57B-A14B / Qwen1.5-MoE-A2.7B even with FSE=1.

Full FSE-vs-this discussion in #43187.

[haofrank]

Hi @mgoin @zyongye, gentle ping on this PR.

This PR is targeting the Qwen2/3-MoE shared-expert gate path and shows measurable E2E throughput improvement on Qwen3-Next-80B-A3B-Instruct-FP8. The bot review comments have been addressed, and I also clarified why this does not overlap with the existing FSE path.

Could one of you help review it, or suggest who would be the right owner for this kernel / Qwen MoE path?

Happy to re-run benchmarks on latest main if needed. Thanks!