[Kernel] Gemma4 MoE decode GEMV optimization — up to 46% TPOT improvement at BS=1-8

[kailashbuki]

[Kernel] Gemma4 MoE decode GEMV optimization — up to 46% TPOT improvement at BS=1-8

Summary

Optimized CUDA GEMV kernels for Gemma4 MoE expert computation during decode. For small-batch decode (T≤8 tokens) where each token independently activates top-8 of 128 experts, per-assignment GEMV with high block-level parallelism achieves 3-5x speedup over the generic Triton fused_experts kernel.

Adaptive dispatch: T≤8 uses CUDA GEMV kernels, T>8 falls back to the default fused_experts path with zero regression.

Key insight

During decode, each MoE expert invocation is a GEMV (matrix-vector multiply) since T=1 per token. The default Triton fused_experts path is optimized for batched GEMM — it groups tokens by expert and amortizes weight loads. But at T≤8 with top-8 routing, there are only 8-64 independent assignments. The Triton kernel launches a few large blocks that underutilize the GPU.

Our approach: launch thousands of small CUDA blocks (one per assignment × column_group). For T=1, K=8, N=352: 8 assignments × 176 column_groups = 1,408 blocks across 132 SMs. Much higher utilization for this workload shape.

The crossover is at T≈16: beyond that, vLLM's Triton kernel wins because it amortizes weight reads across tokens sharing the same expert.

Performance

TP=2 (2× H200, compiled + CUDA graphs)

# Reproduce (torch.compile + CUDA graphs is the default — no --enforce-eager)
vllm bench latency --model google/gemma-4-26B-A4B-it \
    --batch-size <BS> --input-len 128 --output-len 128 \
    --num-iters 30 --tensor-parallel-size 2
# With this PR, dispatch is automatic — same command, no flags needed

BS	Baseline TPOT	Optimized TPOT	Improvement
1	3.93ms	2.82ms	28.2%
2	4.32ms	3.19ms	26.2%
3	5.04ms	3.32ms	34.1%
4	4.96ms	3.28ms	33.8%
8	5.57ms	3.65ms	34.4%
16	6.40ms	6.40ms	0% (fallback)
32	7.75ms	7.60ms	0% (fallback)
64	9.21ms	9.13ms	0% (fallback)

TP=1 (1× H200, compiled + CUDA graphs)

BS	Baseline TPOT	Optimized TPOT	Improvement
1	4.37ms	3.22ms	26.4%
2	5.04ms	3.33ms	34.0%
3	6.43ms	3.46ms	46.2%
4	6.39ms	3.48ms	45.5%
8	6.81ms	3.74ms	45.1%

TP=1 shows larger improvements (up to 46%) because MoE is a bigger fraction of total decode time without allreduce overhead.

Isolated MoE block (microbenchmark)

Tokens	Optimized (μs)	Baseline (μs)	Speedup
1	70	375	5.3×
2	102	383	3.7×
4	167	373	2.2×
8	293	412	1.4×
16	547	457	0.8× (baseline wins)

Benchmark environment

• GPU: NVIDIA H200 SXM (141GB HBM3e, 4.8 TB/s)
• vLLM: built from source (commit 2c06cf3), CUDA 12.8, PyTorch 2.11.0
• Mode: torch.compile + CUDA graphs (vLLM default, NOT --enforce-eager)
• Model: google/gemma-4-26B-A4B-it (128 experts, top-8, H=2816, BF16)

How it works

Three-phase CUDA pipeline per MoE layer:

1. Gate+Up GEMV (gemma4_gate_up_gemv): Each thread block computes 4 output columns for one (token, expert) assignment. 256 threads partition the H=2816 reduction dimension, with warp shuffle + cross-warp shared memory reduction.

2. GELU activation (gemma4_gelu_mul_kernel): Elementwise GELU(gate) * up using tanh approximation.

3. Down GEMV (gemma4_down_gemv): Same blocking as gate_up. Uses atomicAdd weighted by routing weights to accumulate expert contributions per token.

Routing is a separate warp-cooperative kernel: each warp handles one token's softmax → top-K → renormalize → per_expert_scale, all in registers (128 experts = 4 values per thread).

Dispatch happens inside MoERunner._forward_impl() (within the moe_forward custom op boundary), so torch.compile never sees the dispatch code and CUDA graphs capture the kernel launches correctly.

Accuracy (lm-eval-harness)

No quality regression on standard benchmarks.

TP=1 (bit-for-bit identical — deterministic log-likelihood evaluation):

Dataset	Metric	Baseline	Kernel	Delta
HellaSwag (10k)	acc_norm	0.4290	0.4290	0.0000
ARC-Easy (2.4k)	acc	0.3620	0.3620	0.0000

TP=2 (within statistical noise — allreduce introduces nondeterministic ordering):

Dataset	Metric	Baseline	Kernel	Delta	Stderr
HellaSwag (10k)	acc_norm	0.4277	0.4301	+0.0024	±0.0049
ARC-Easy (2.4k)	acc	0.3725	0.3733	+0.0008	±0.0099

# Reproduce:
lm_eval --model vllm \
    --model_args pretrained=google/gemma-4-26B-A4B-it,tensor_parallel_size=1,gpu_memory_utilization=0.9 \
    --tasks hellaswag,arc_easy --batch_size auto

Scope and limitations

• Gemma4 only: The adaptive dispatch detects Gemma4's specific properties (E≥64 experts, per_expert_scale in routing closure, bf16 weights). Other MoE models (Mixtral, DeepSeek, Llama-4) are unaffected.
• Decode only (T≤8): Falls back to the default fused_experts path for T>8 with zero regression.
• Hopper only: CUDA kernels target SM 9.0a (H100/H200). Other architectures use the default path.
• BF16 weights only: The GEMV kernels use bf16×bf16→fp32 accumulation. FP8 quantized models use the default FP8 path.

Files changed

New CUDA kernels (csrc/moe/gemma4_decode/):

• gemma4_moe_decode.cu — Expert GEMV kernels (gate_up + GELU + down)
• gemma4_routing.cu — Warp-cooperative routing kernel
• moe_ops.h — C++ declarations

Integration:

• csrc/moe/torch_bindings.cpp — Op registration
• csrc/moe/moe_ops.h — Declarations
• CMakeLists.txt — Build rules for SM90+
• vllm/.../fused_moe/gemma4_moe_decode.py — Python dispatch (CMake or JIT)
• vllm/.../fused_moe/runner/moe_runner.py — Adaptive dispatch in _forward_impl

Tests:

• tests/kernels/moe/test_gemma4_moe_decode.py — Correctness vs PyTorch reference

Test plan

• Expert GEMV correctness vs PyTorch reference at T=1,2,4,8 (max error <1.5e-04)
• Routing matches reference gemma4_routing_function_torch
• Correct generation with chat template at TP=1 and TP=2
• No regression at BS>8 (falls back to default)
• Pre-commit passes
• vllm bench latency improvement at BS=1-8, TP=1 and TP=2
• lm-eval accuracy: HellaSwag + ARC-Easy identical at TP=1, within noise at TP=2

Duplicate-work check

No existing open PR addresses Gemma4 MoE decode GEMV optimization:

gh pr list --repo vllm-project/vllm --state open --search "gemma4 moe decode"
gh pr list --repo vllm-project/vllm --state open --search "gemma4 GEMV"

PR #40565 (routing int64 dtype) and #40542 (MoE tuning configs) are unrelated.

AI-Assisted Contributions

This kernel was developed with assistance from Claude Code (Anthropic). The human submitter (@kailashbuki) directed the optimization strategy, reviewed all kernel code and integration logic, validated correctness and performance, and can defend every design decision. All changed lines have been reviewed. Test commands and results are documented above.

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Code Review

This pull request introduces optimized CUDA GEMV kernels for Gemma4 MoE decode operations with small batch sizes (T <= 8), significantly improving SM utilization compared to generic Triton implementations. The feedback recommends using a WeakKeyDictionary for caching scaling factors in the MoE runner to prevent memory leaks and potential issues with object ID reuse. Additionally, the reviewer suggests enforcing strict limits on the number of experts and top_k within the Python dispatch logic to prevent buffer overflows in the CUDA kernels and removing a redundant variable assignment.