[Kernel] Tune default fp8 block-scaled Triton config for M<=8 decode

[tonyliu312]

Purpose

w8a8_triton_block_scaled_mm falls back to a hardcoded default config when no pre-tuned configs/N=*,K=*,device_name=*.json file matches the GPU. The default uses BLOCK_SIZE_M=64, which wastes 98% of the M dimension for single-request decode (M=1). GPUs without a pre-tuned JSON for their (N, K) tuple pay this cost.

This PR specializes only the M ≤ 8 branch (single-request decode and short MTP-style draft batches) to use BLOCK_SIZE_M=16, num_stages=3. Larger M is unchanged to keep blast radius small.

M range	BLOCK_SIZE_M	num_stages
M <= 8	16	3 (new)
else	64 (unchanged)	2 (unchanged)

Pre-tuned JSON configs are unaffected — they short-circuit before this branch. Workloads that already have a tuned JSON for their (N, K, device) keep the exact same kernel as before.

Test Plan

1. On a host without a pre-tuned JSON for the (N, K, device) of the model under test, run single-request fp8 block-scaled decode at M=1.
2. Measure median tokens/sec over a steady-state window.
3. Verify output text is coherent.
4. Confirm no behavioral change for prefill (large M) or for hosts with a pre-tuned JSON.

Test Result

Hardware: dual DGX Spark (GB10, sm_121), TP=2. Model: DeepSeek-V4-Flash. Mode: single request, decode-dominated.

	Before (BLOCK_SIZE_M=64 default)	After (M ≤ 8 specialised)
Median decode throughput	5.45 t/s	6.73 t/s
Speedup	—	+23%
Output coherence	OK	OK

Run config: --moe-backend marlin --kv-cache-dtype fp8_ds_mla --gpu-memory-utilization 0.88 --load-format instanttensor, max_tokens=80, temperature=0, 5 warm runs, statistical median.

No-regression check: for M ≥ 9 the patch falls into the existing else branch with BLOCK_SIZE_M=64, num_stages=2, matching the prior default exactly. For hosts with a tuned JSON, the if configs: branch fires and this code path is never reached.

Notes

• Scope deliberately narrow: only M <= 8 is changed. M > 8 keeps the previous default. This is intentionally smaller than my first internal draft (which also added an M ≤ 32 branch) to minimise risk on archs where I don't have a way to verify (Hopper / Ampere / Datacenter Blackwell).
• Cross-arch claim is honest: the win is measured only on GB10 (sm_121). The 98%-of-M-dim waste argument generalises (any decoder with M=1 single-request load lacking a tuned JSON), but I cannot verify on Hopper/Ampere from this hardware. Reviewers on those archs are welcome to push back or confirm. If a regression is found on a specific arch, narrowing to if capability_family == 12 is straightforward.
• num_stages=3 for the M ≤ 8 branch is the local optimum from a short autotune sweep on GB10. On Hopper, num_stages can interact with shared-mem occupancy. If this regresses, the safe fallback is to keep num_stages=2 in the M ≤ 8 branch (BLOCK_M=16 alone still recovers most of the win).
• Conservative: I deliberately do not change BLOCK_SIZE_N, BLOCK_SIZE_K, GROUP_SIZE_M, or num_warps, because changing them has second-order effects that vary by arch.

Related

• Refs [Feat] DeepSeek V4 Rebased  #40860 (ivanium V4 Rebased) — orthogonal scope
• Refs DeepSeek V4 support on SM12x with Triton sparse MLA fallback #40899 (jasl ds4-sm120) — orthogonal scope; that PR fixes SM 12.x kernel selection, this PR is a generic decode-config improvement
• Per-arch tuned JSONs are the right long-term answer — those still belong in configs/N=*,K=*,device_name=*.json files, not in this default branch.

Checklist

• Tested on real hardware (GB10 / DGX Spark, sm_121, TP=2)
• No change for M > 8 (existing default preserved)
• No change when a tuned JSON config is present (short-circuited above)
• Commit signed-off (DCO)
• Pre-commit lint run locally (pre-commit run --files vllm/model_executor/layers/quantization/utils/fp8_utils.py)
• CI passes (will be confirmed once submitted; pending ready label from maintainer per first-time-contributor gate)

[claude]

Claude Code Review

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[gemini-code-assist]

Code Review

This pull request optimizes the w8a8_triton_block_scaled_mm Triton kernel for low-M decode scenarios by adjusting BLOCK_SIZE_M and num_stages when M <= 8. A review comment points out that setting num_stages to 3 can lead to resource exhaustion on ROCm platforms and suggests using a platform-specific configuration to maintain stability.

[gemini-code-assist]

Setting num_stages=3 can lead to OutOfResources errors or performance regressions on ROCm, as seen in other Triton kernels in the codebase (e.g., in vllm/model_executor/layers/fused_moe/fused_moe.py). It is safer to use num_stages=2 for ROCm while keeping the optimized value for NVIDIA architectures.

Suggested change

	if M <= 8:
	block_m, num_stages = 16, 3
	else:
	block_m, num_stages = 64, 2
	if M <= 8:
	block_m, num_stages = 16, (2 if current_platform.is_rocm() else 3)
	else:
	block_m, num_stages = 64, 2

[tonyliu312]

Hi @mgoin @tlrmchlsmth — this is my first vLLM contribution, so the pre-run-check workflow is currently blocked on the first-time-contributor ready label gate (no merged PRs yet on this account, so CI never runs the actual checks).

Would one of you (or any quantization CODEOWNER) be willing to take a quick look and add the ready label if it looks reasonable? It's a small change (10 lines added, 2 removed) inside the else branch of w8a8_triton_block_scaled_mm's default-config fallback — only applied when no pre-tuned configs/N=*,K=*,device_name=*.json matches the GPU. The branch is intentionally narrow: only M <= 8 is specialised (BLOCK_SIZE_M=16, num_stages=3); larger M keeps the previous default exactly. Verified +23% on GB10 single-request decode (5.45 → 6.73 t/s) for V4-Flash, with no regression possible for M > 8 or for hosts that already hit a tuned JSON.

Happy to address any review feedback. Thanks for your time!

[tonyliu312]

Thanks for catching this @gemini-code-assist — you're right.

w8a8_triton_block_scaled_mm is a platform-agnostic op (registered via torch.ops.vllm.w8a8_triton_block_scaled_mm_func), and 3-stage pipelining at the typical [128, 128] block sizes is borderline for MI300/MI250X LDS (64 KB).

Just amended the commit (force-pushed da10c6e) to gate num_stages=3 to non-ROCm:

if M <= 8:
    block_m = 16
    num_stages = 2 if current_platform.is_rocm() else 3
else:
    block_m, num_stages = 64, 2

Rationale: the BLOCK_SIZE_M=16 wave-quantisation win is the dominant effect for low-M decode (most of the +23% on GB10). num_stages=3 is the smaller second-order win specific to CUDA. On ROCm we keep num_stages=2 so the M≤8 branch still recovers the bulk of the gain without LDS pressure. Commit message updated accordingly.

[gemini-code-assist]

Thanks for the update, @tonyliu312. The change to gate num_stages=3 to non-ROCm platforms is a prudent adjustment given the LDS constraints on MI300/MI250X. This approach maintains the performance gains for the M <= 8 case while ensuring stability across different hardware architectures. The logic looks sound.