[RFC] Add CUDA-native GDN decode kernel as Blackwell fallback

[ssubbotin]

Summary

Adds a CUDA-native single-token decode kernel for Gated DeltaNet (GDN) linear attention, providing a Triton-free decode path. This is primarily motivated by Blackwell SM 12.0 compatibility, where the Triton FLA autotuner can deadlock or OOM during kernel warmup.

Motivation

On Blackwell GPUs (RTX PRO 6000, RTX 5090), running MoE+Mamba models like Qwen3-Coder-Next through the Triton FLA path fails due to:

1. Triton global_scratch allocator crash — Blackwell kernels use global_scratch memory, but Triton raises RuntimeError when no allocator is set (upstream fix: Add default global_scratch allocator fallback for Blackwell SM 12.0 triton-lang/triton#10002)
2. Autotuner deadlock — Even with the allocator fix, the FLA solve_tril autotuner can deadlock during warmup (futex_wait_queue)
3. Hopper misclassification — SM 12.0 triggers is_nvidia_hopper checks designed for SM 9.0 ([Bugfix] Disable TMA on Blackwell GPUs to fix Triton autotuner OOM in fla/solve_trilfix: disable TMA on Blackwell (sm_12x) to prevent Triton autotuner OO… #36325, [Bugfix] Fix FLA Hopper/TMA misclassification on SM12x desktop Blackwell #37700)

A CUDA-native kernel bypasses all three issues — no Triton JIT, no autotuner, no architecture detection.

Implementation

The kernel implements the GDN recurrence in ~100 lines of CUDA:

h *= exp(g)                  # state decay
v -= sum(h * k, dim=k)       # project state onto key
v *= sigmoid(b)              # beta gating  
h += outer(v, k)             # update state
o = sum(h * q, dim=k)        # output projection

Adapted from the flash-moe project's gated_delta_net_step kernel, which runs Qwen3.5-397B-A17B at 7.19 tok/s on RTX PRO 6000 Blackwell — the fastest published result for this model.

Key properties:

• Parameterized for arbitrary head dimensions (not hardcoded)
• Supports GQA (grouped query attention) head mapping
• Supports L2 normalization of Q/K in-kernel
• Integrates with vLLM's state cache indexing for continuous batching
• Handles PAD_SLOT_ID (-1) for padding
• All computation in fp32 (matching the Triton kernel)

Files changed:

• csrc/mamba/gdn_decode_kernels.cu — CUDA kernel (193 lines)
• csrc/ops.h — function declaration
• csrc/torch_bindings.cpp — torch.ops.vllm.gdn_decode_step registration
• CMakeLists.txt — build config

Status: RFC

This PR adds the kernel and build integration. Not yet wired into the GDN layer — the Python-side integration (backend selection in gdn_linear_attn.py, --gdn-decode-backend cuda config option) is a follow-up. Posting as RFC to get feedback on the kernel design before adding the wiring.

Related Issues

• [Bugfix] Disable TMA on Blackwell GPUs to fix Triton autotuner OOM in fla/solve_trilfix: disable TMA on Blackwell (sm_12x) to prevent Triton autotuner OO… #36325 — TMA on Blackwell OOM
• [Bugfix] Fix FLA Hopper/TMA misclassification on SM12x desktop Blackwell #37700 — FLA Hopper/TMA misclassification on SM12x
• Add default global_scratch allocator fallback for Blackwell SM 12.0 triton-lang/triton#10002 — Root cause fix for global_scratch allocator

Testing

Kernel logic verified via the flash-moe project on:

• RTX PRO 6000 Blackwell (SM 12.0, CUDA 13.1) — 7.19 tok/s on Qwen3.5-397B
• RTX 4090 Ada (SM 8.9, CUDA 12.8) — 4.36 tok/s on Qwen3.5-397B

Not yet integration-tested within vLLM (pending Python-side wiring).

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[gemini-code-assist]

Code Review

This pull request adds a CUDA-native GDN (Gated DeltaNet) single-token decode kernel for vLLM, providing a Triton-free path for Blackwell and other GPUs. The implementation includes the CUDA kernel, C++ headers, and Torch bindings. The review identified a critical bug where early thread returns interfere with synchronization barriers, potentially causing deadlocks. Additionally, a type mismatch between the kernel and Python-side buffers was noted, which could lead to memory corruption. Performance concerns were also raised regarding the serialized reduction logic and the overhead of per-step type conversions and contiguity operations.

[gemini-code-assist]

This early return is a critical bug that will lead to deadlocks or undefined behavior. In CUDA, __syncthreads() must be reached by all threads in a block. Since the block size is fixed at 128 or 256 in the dispatch logic but head_k_dim can be any value up to 256, threads where k_idx >= head_k_dim will exit early, while the remaining threads will hang at the subsequent barriers (e.g., lines 65, 71, 109, etc.). You should remove the early return and instead wrap the thread-specific work in a conditional block, ensuring all threads reach the synchronization points.

[gemini-code-assist]

The kernel assumes that the output tensor is of type float (FP32), but the Python-side integration in vllm/model_executor/layers/mamba/gdn_linear_attn.py (line 565) creates the output buffer using hidden_states.dtype, which is typically float16 or bfloat16. Passing a half-precision pointer to a kernel expecting float* will result in memory corruption and incorrect results. You must ensure the output tensor is FP32 or update the kernel to handle half-precision types.

[gemini-code-assist]

The reduction implementation is highly inefficient for a performance-oriented kernel. Having thread 0 perform a serial loop over head_k_dim elements while the rest of the block waits at a barrier creates a significant bottleneck, especially since this pattern is repeated multiple times inside the vi loop. This serial bottleneck negates much of the benefit of using a custom CUDA kernel for decoding.

[gemini-code-assist]

Performing type conversion and making tensors contiguous on every decode step is expensive due to repeated memory allocations and synchronous copies. For a single-token decode kernel, these overheads can dominate the execution time and increase latency. The kernel should ideally be templated to support half and nv_bfloat16 types directly for inputs to avoid these per-step conversions.

[ZJY0516]

we have disable TMA by default now, see #38981

[ZJY0516]

Autotuner deadlock — Even with the allocator fix, the FLA solve_tril autotuner can deadlock during warmup (futex_wait_queue)

Do you have any reproduce script?

[ssubbotin]

Blackwell Test Results (RTX PRO 6000, SM 12.0, CUDA 13.1)

Added scripts/reproduce_blackwell_gdn.py for easy reproduction and verification.

Correctness (vs PyTorch reference):

PASS: Qwen3.5-397B single            out_diff=0.000001 state_diff=0.000001
PASS: Qwen3.5-397B batch=4           out_diff=0.000002 state_diff=0.000001
PASS: Medium model                   out_diff=0.000001 state_diff=0.000001
PASS: Small model batch=8            out_diff=0.000002 state_diff=0.000001
PASS: PAD_SLOT_ID (-1) handling

Benchmark (CUDA GDN decode kernel):

batch= 1:    115.9 µs/step (8629 steps/s)
batch= 4:    116.9 µs/step (8555 steps/s)
batch= 8:    116.8 µs/step (8558 steps/s)

Scales flat with batch size — GPU-bound, not memory-bound. Kernel adapted from flash-moe which runs Qwen3.5-397B at 7.19 tok/s on this hardware.

[ssubbotin]

@ZJY0516 Here's the reproduce script for the Blackwell deadlock: https://gist.github.com/ssubbotin/2cfa8ac4f3904df66872a882e44eeb86

Standalone — requires only torch + triton + vLLM installed, no model download needed.

# Reproduce (crashes on Blackwell, hangs inside autotuner during real model load):
python reproduce_blackwell_deadlock.py

# With the Triton allocator fix:
python reproduce_blackwell_deadlock.py --fix

Results on RTX PRO 6000 Blackwell (SM 12.0, CUDA 13.1, Triton 3.6.0):

Without fix:

Test 1: FLA chunk_gated_delta_rule (prefill path)...
  CRASH: Kernel requires a runtime memory allocation, but no allocator was set.

With --fix (applies triton.set_allocator workaround):

Test 1: FLA chunk_gated_delta_rule (prefill path)...
  PASS (27.2s, output shape torch.Size([1, 128, 8, 128]))

The 27.2s is the one-time Triton JIT compilation cost. On subsequent runs the compiled kernel is cached.

The root cause is that Blackwell kernels use global_scratch memory, but Triton's NullAllocator raises RuntimeError instead of allocating. During real model loading, this crash happens inside the Triton autotuner's _bench() which catches it, corrupting CUDA sync state → deadlock (futex_wait_queue).

Also pushed fixes for the code review comments (warp-level reduction, syncthreads safety, fp32 output check).

[ssubbotin]

@ZJY0516 To clarify — disabling TMA (#38981) does not fix the Blackwell issue. The crash happens on the non-TMA code path too.

Here's the proof from our reproduce script on RTX PRO 6000 Blackwell (SM 12.0), using the unpatched vllm/vllm-openai:gemma4 image where FLA_USE_TMA=0 (TMA already off):

$ python reproduce_blackwell_deadlock.py

GPU:       NVIDIA RTX PRO 6000 Blackwell Workstation Edition
SM:        12.0

Test 1: FLA chunk_gated_delta_rule (prefill path)...
  CRASH: Kernel requires a runtime memory allocation, but no allocator was set.

The root cause is deeper than TMA: any Triton kernel that compiles to use global_scratch memory fails on Blackwell because Triton's NullAllocator raises RuntimeError instead of allocating. The FLA solve_tril kernel uses global_scratch on SM 12.0 even with TMA disabled.

This means MoE+Mamba models (Qwen3-Coder-Next, Qwen3.5) cannot run on any Blackwell GPU with current vLLM, regardless of TMA settings.

Our PR provides:

1. A CUDA-native GDN decode kernel that bypasses Triton entirely (tested at 8.4 tok/s with Qwen3-Coder-Next on Blackwell)
2. An upstream Triton fix for the allocator (Add default global_scratch allocator fallback for Blackwell SM 12.0 triton-lang/triton#10002)
3. A reproduce script to verify on any Blackwell hardware

[ssubbotin]

Update: CUDA graphs work on Blackwell with the Triton fix

Removed --enforce-eager from our patched Docker image (which includes the Triton allocator fix from triton-lang/triton#10002). Result:

Mode	tok/s	Speedup
--enforce-eager	13.3	1x
CUDA graphs + torch.compile	156.4	12x

Model: Qwen3-Coder-Next 80B (AWQ 4-bit), GPU: RTX PRO 6000 Blackwell (SM 12.0)

The --enforce-eager workaround recommended in various Blackwell issues costs 12x performance. The Triton allocator fix (triton-lang/triton#10002) restores full CUDA graph support, making the workaround unnecessary.

This further validates why the CUDA GDN decode kernel in this PR is valuable — it provides a Triton-free path that works even without the upstream Triton fix.

[ssubbotin]

Closing this PR. After benchmarking, the CUDA-native GDN kernel is 3.2x slower than the Triton FLA kernel on Blackwell (65.6 µs vs 20.4 µs per decode step). The Triton autotuner finds configurations our simple kernel can't match.

The real fix is the Triton allocator patch (triton-lang/triton#10002), which:

• Unblocks CUDA graphs on Blackwell → 12x speedup (13 → 156 tok/s)
• Lets the existing Triton FLA kernels work without modification
• Is a 24-line change in Triton, not a new kernel in vLLM

The reproduce script and root cause analysis remain available:

• Gist: https://gist.github.com/ssubbotin/2cfa8ac4f3904df66872a882e44eeb86
• Root cause: Triton allocate_scratch in driver.py raises RuntimeError on Blackwell SM 12.0 when global_scratch memory is needed but no allocator is configured. This crashes the FLA solve_tril autotuner, which corrupts CUDA sync state → deadlock. --enforce-eager works around it at 12x performance cost.

All effort should go toward merging triton-lang/triton#10002.