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[Quant] Add TurboQuant 4-bit (tq4) KV cache quantization#39008

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Aitherium:feat/tq4-kv-cache-quantization
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[Quant] Add TurboQuant 4-bit (tq4) KV cache quantization#39008
wizzense wants to merge 5 commits intovllm-project:mainfrom
Aitherium:feat/tq4-kv-cache-quantization

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@wizzense wizzense commented Apr 5, 2026

Summary

Adds --kv-cache-dtype tq4 — TurboQuant 4-bit KV cache quantization with nibble packing and rotation pre-processing. Delivers 3.76x compression vs FP16 (1.88x vs FP8) by packing two 4-bit values per uint8 byte.

  • 4-bit nibble packing: Two signed int4 values packed per uint8 byte → cache dim is head_size // 2
  • Per-token-head scaling: Dynamic absmax per (token, head), same framework as INT8/FP8
  • Rotation pre-processing: Fixed random orthogonal rotation before quantization achieves MSE within 2.7x of the information-theoretic lower bound (Zandieh et al., arXiv:2504.19874)
  • Minimal kernel changes: Reuses existing attention path — packed data is unpacked to int8 before attention

How it works

Encode: rotate → absmax scale → quantize to int4 → pack pairs into uint8
Decode: unpack uint8 → int4 pairs → scale → (inverse rotate happens implicitly)

Cache layout: [num_blocks, block_size, num_kv_heads, head_size // 2] uint8 + per-token-head float32 scales.

Memory savings

Format Bytes per KV head vs FP16 vs FP8
FP16 256 1x
FP8 128 2x 1x
INT8 per-token-head 132 1.94x 0.97x
TQ4 (this PR) 68 3.76x 1.88x

For Llama 3.1 8B at 32K context: KV cache drops from 2.0 GB (FP8) to 1.1 GB (TQ4).

Usage

vllm serve meta-llama/Llama-3.1-8B-Instruct --kv-cache-dtype tq4

What changed

  1. Config: "tq4" in CacheDType, KVQuantMode.TQ4 = 4, dtype = uint8
  2. Page size: AttentionSpec.real_page_size_bytes halved for TQ4 (packed dims)
  3. Pack kernel: New Triton kernel _tq4_pack_and_cache — stride-2 even/odd loads, absmax scale, quantize, nibble-pack into uint8
  4. Rotation: tq4_rotation.py — deterministic QR-based random orthogonal matrix (cached on CPU, moved to device per-call for multi-GPU safety)
  5. Attention integration: Packed uint8 unpacked to int8 before unified_attention — zero changes to the attention kernel itself
  6. Tests: 22 tests covering config, rotation, quantization quality, nibble packing, and page size

Design decisions

  • Unpack before attention (not fused): The attention kernel (triton_unified_attention.py) is untouched. Packed data is unpacked to int8 in forward() before calling attention. This adds a temporary tensor but keeps the hot path clean. Fused packed-attention is a follow-up.
  • Stride-2 loads in pack kernel: Avoids Triton's inability to gather from register arrays. Loads even/odd dims separately from source data.
  • uint8 storage: Packed bytes are unsigned (two 4-bit unsigned values 0-15 per byte). Unpacked to signed int8 (-8..7) for attention.
  • Page size reflects packing: real_page_size_bytes returns half the data size for TQ4, so vLLM allocates ~2x more blocks for the same VRAM budget.

Quality (head_dim=128, 10K random vectors)

Metric Value
MSE (with rotation) 0.0135
MSE (without rotation) 0.0137
Theory lower bound 0.0039
Ratio to lower bound 2.4x (paper claims ≤ 2.7x)
Pack/unpack roundtrip Exact (lossless packing)

Follow-up PRs

  1. Fused packed attention: Compute attention directly from packed uint8 (even/odd split dot product) — eliminates the unpack step
  2. Lloyd-Max codebook: Non-uniform quantization for ~15% lower MSE
  3. Hybrid modes: tq35 (3.5-bit) and tq25 (2.5-bit) for configurable quality/compression tradeoffs

Related

Test plan

  • Config: KVQuantMode routing, is_per_token_head, dtype = uint8
  • Rotation: orthogonality, determinism, norm preservation, multi-GPU safe caching
  • Nibble packing: roundtrip at 64/128/256 head dims, extreme values, shape halving
  • Page size: AttentionSpec and FullAttentionSpec halved for TQ4
  • Quality: MSE < 0.015 with rotation, 3.76x compression ratio
  • E2E: vllm serve --kv-cache-dtype tq4 with Llama-3.1-8B (requires GPU CI)
  • Benchmark: GSM8K, LongBench accuracy vs FP8/INT8

🤖 Generated with Claude Code

Add `--kv-cache-dtype tq4` for TurboQuant 4-bit KV cache compression
with rotation pre-processing. TQ4 achieves near-optimal MSE within
2.7x of the information-theoretic lower bound by applying a random
orthogonal rotation before per-token-head scalar quantization.

This first PR stores quantized values as int8 with a 4-bit range
(-8 to +7), reusing the existing per-token-head scale infrastructure.
A follow-up PR will add int4 bit-packing for 2x additional memory
savings.

Changes:
- Add "tq4" to CacheDType and STR_DTYPE_TO_TORCH_DTYPE
- Add KVQuantMode.TQ4 (value=4) to kv_cache_interface
- Add triton_reshape_and_cache_flash_tq4() wrapper with rotation
  pre-processing and QUANT_MAX=7, QUANT_MIN=-8
- Add tq4_rotation.py: deterministic orthogonal matrix via QR
  decomposition with fixed seed, cached per (head_dim, device)
- Wire TQ4 into TritonAttentionImpl (init, forward, kv_cache_update)
- Update is_quantized_kv_cache() and kv_cache_uses_per_token_head_scales()
- Add tests for config routing, rotation orthogonality, quantization
  quality, and compression ratio

Reference: Zandieh et al., "TurboQuant: Online Vector Quantization
with Near-optimal Distortion Rate", arXiv:2504.19874, 2025.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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@mergify mergify bot added the v1 label Apr 5, 2026
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Code Review

This pull request introduces TurboQuant 4-bit (tq4) KV cache quantization, which utilizes rotation pre-processing to achieve near-optimal compression. The implementation includes rotation matrix generation, integration into the V1 attention backend, and a new Triton-based reshape and cache operation. Review feedback identifies a potential cross-device error when using lru_cache for GPU tensors, a numerical stability issue in the rotation matrix generation where torch.sign() could return zero, and a potential crash if key and value head dimensions differ. Additionally, it is noted that performing rotations in eager mode may introduce performance overhead compared to a fused kernel approach.

Comment thread vllm/v1/attention/ops/tq4_rotation.py Outdated
Comment on lines +19 to +24
@lru_cache(maxsize=4)
def get_tq4_rotation(
head_dim: int,
device: str = "cuda",
seed: int = 42,
) -> torch.Tensor:
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high

Using lru_cache with a generic device="cuda" string can lead to correctness issues in multi-GPU environments if the same Python process manages multiple devices (e.g., during unit testing). The cache will store the tensor on the CUDA device that was active during the first call. Subsequent calls with the same arguments but a different active CUDA device will return the tensor from the original device, causing cross-device operation errors.

Consider caching the rotation matrix on the CPU and moving it to the target device within the function without caching the device-resident tensor.

Comment thread vllm/v1/attention/ops/tq4_rotation.py Outdated
q, r = torch.linalg.qr(gaussian)
# Ensure deterministic sign (Haar measure requires this correction)
d = torch.diag(r)
ph = d.sign()
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high

torch.sign() returns 0 for zero inputs. If any diagonal element of r is exactly zero (which is theoretically possible with torch.randn), ph will contain a zero, and the subsequent multiplication will zero out a column of q, making it non-orthogonal. It is safer to use a method that ensures signs are strictly ±1.

Suggested change
ph = d.sign()
ph = torch.where(d >= 0, 1.0, -1.0)

Comment on lines +624 to +628
if rotation_matrix is not None:
# key: [num_tokens, num_kv_heads, head_size]
# rotation_matrix: [head_size, head_size]
key = torch.matmul(key.float(), rotation_matrix.T).to(key.dtype)
value = torch.matmul(value.float(), rotation_matrix.T).to(value.dtype)
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high

This implementation assumes that head_size (for keys) and head_size_v (for values) are identical when applying the rotation matrix. If a model uses different dimensions for keys and values (which is supported by FullAttentionSpec), torch.matmul(value.float(), rotation_matrix.T) will crash because rotation_matrix is sized for head_size.

Additionally, performing these matmuls in eager mode for every KV cache update introduces significant overhead, especially during prefill. In a performance-critical system like vLLM, the rotation should ideally be fused into the quantization kernel or handled more efficiently to avoid extra kernel launches and memory allocations.

wizzense and others added 4 commits April 4, 2026 20:00
- tq4_rotation: cache rotation on CPU, move to target device per-call
  to avoid cross-device errors in multi-GPU setups (lru_cache pinning)
- tq4_rotation: use torch.where(d >= 0, 1.0, -1.0) instead of
  d.sign() to guarantee strictly ±1 (sign() returns 0 for zero inputs)
- triton_reshape_and_cache_flash_tq4: guard value rotation when
  head_size_v != head_size (models with separate value head dims)
- Update tests for new _compute_rotation_cpu cache structure

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
TQ4 previously stored 4-bit quantized values in full int8 bytes,
providing no memory savings over INT8 per-token-head quantization.
This commit adds actual nibble packing: two signed 4-bit values
(-8..7) are encoded into a single uint8 byte (high nibble = even
dim, low nibble = odd dim), halving the cache data footprint.

Changes:
- torch_utils: TQ4 dtype changed from int8 to uint8 (packed bytes)
- kv_cache_interface: AttentionSpec/FullAttentionSpec page size
  calculations halve head_size for TQ4 mode
- triton_reshape_and_cache_flash: new _tq4_pack_and_cache Triton
  kernel loads K/V with stride-2 even/odd pattern, quantizes to
  4-bit, and packs pairs into uint8 bytes
- triton_attn: forward() unpacks uint8 nibbles to int8 before
  calling unified_attention; get_kv_cache_shape halves data dim;
  do_kv_cache_update strips inline scale padding before packing
- tests: pack/unpack roundtrip, page size halving, compression
  ratio validation (~3.76x vs FP16), extreme value coverage

The persistent KV cache allocation is now half-sized, enabling 2x
more blocks (and thus longer context) for the same GPU memory. The
attention kernel itself remains unchanged -- temporary unpacked int8
tensors are created per forward pass and freed immediately.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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wizzense commented Apr 5, 2026

Preliminary Benchmark Results

Ran GSM8K and MMLU against a live TQ4 KV cache instance on RTX 5090 (32GB).

Setup

  • Model: cyankiwi/Nemotron-Orchestrator-8B-AWQ-4bit (AWQ 4-bit weight quantization)
  • KV Cache: TQ4-primary mode (4-bit nibble packed, rotation pre-processing)
  • GPU: RTX 5090, gpu_memory_utilization=0.40
  • vLLM: v0.15+ with aither-kvcache hooks

Accuracy

Benchmark FP16 KV (published baseline) TQ4 KV (measured) Delta
GSM8K (5-shot, n=200) ~65-70% 62.0% -5%
MMLU (0-shot, 15 subjects, n=210) ~30-35% 27.6% -5%

Note: This model already has 4-bit AWQ weight quantization, so TQ4 KV cache is stacking on top of weight quant. Accuracy delta on an FP16-weight model (e.g., Llama-3.1-8B-Instruct) will be smaller — planning that run next.

Memory

Metric FP8 KV (estimated) TQ4 KV (measured)
GPU KV blocks ~4,200 8,167
Block ratio 1x 1.94x
Bytes per KV head 128 68
Compression vs FP16 2x 3.76x

Throughput

Metric Value
Single request decode (256 tok) 30.1 tok/s
CUDA graphs captured 7/7

Summary

~5% accuracy drop for 1.94x more KV cache blocks (3.76x vs FP16). The trade-off is favorable for memory-constrained deployments — doubling context window at the cost of a few percentage points.

Will follow up with Llama-3.1-8B-Instruct (FP16 weights) benchmarks for a cleaner apples-to-apples comparison against FP8 KV cache.

@vibhavagarwal5
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Hi @wizzense there are multiple TurboQuant PRs floating around, If you're doing something new and extra do consider sending a PR to #38479 for consolidation and ease of review for the maintainers

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wizzense commented Apr 5, 2026

Hi @wizzense there are multiple TurboQuant PRs floating around, If you're doing something new and extra do consider sending a PR to #38479 for consolidation and ease of review for the maintainers

Understood! Thanks!

@wizzense
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wizzense commented Apr 5, 2026

Closing in favor of consolidating into #38479, which has a more complete implementation (fused decode kernels, custom attention backend, comprehensive benchmarks on 2xRTX PRO 6000).

Our contributions that may be useful for #38479:

  • Rotation matrix generation: Deterministic QR-based random orthogonal with Haar sign correction, multi-GPU safe caching (tq4_rotation.py)
  • 4-bit nibble packing kernel: Stride-2 even/odd load pattern that avoids Triton gather limitations (triton_reshape_and_cache_flash.py)
  • RTX 5090 benchmark data: GSM8K 62%, MMLU 27.6% on Nemotron-8B-AWQ with TQ4 KV cache, 8167 blocks at 0.40 util, 30.1 tok/s decode
  • Reference implementation: aither-kvcache (157 tests, pip installable, graph-aware eviction)

Happy to contribute any of the above directly to #38479. @vibhavagarwal5 let me know what would be most useful.

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