[ROCm][Kernel] Add GFX11 (RDNA3) support for wvSplitK skinny GEMM kernels

[mgehre-amd]

Summary

Enable the wvSplitK skinny GEMM kernels on all GFX11 (RDNA3) GPUs. These kernels accelerate decode-phase GEMMs (small batch size, large K) by using wave-level split-K with butterfly reduction.

Key adaptations for RDNA's wave32 execution model:

• Use v_dot2acc_f32_f16 (renamed from v_dot2c_f32_f16 on GFX11)
• Wave32 butterfly reduction via __shfl_xor instead of GFX9's DPP row_shr
• Use THRDS=32 on GFX11 (one wavefront per row); keep THRDS=64 on GFX9
• Add is_gfx11() runtime helper for host-side kernel dispatch
• Add on_gfx11() helper and use on_gfx9() or on_gfx11() to gate the Python dispatch path
• Relax wvSplitK test tolerance to account for fp16 accumulation error scaling with sqrt(K)

Performance

Benchmarked on AMD Strix Halo (gfx1151, LPDDR5X-8000 128 GB):

Qwen/Qwen3-4B (bf16, unquantized) — decode TPOT ~20% faster:

Workload	Metric	Baseline	Optimized	Change
input=128, output=128	Median TPOT	50.03 ms	40.18 ms	19.7% faster
input=1920, output=128	Median TPOT	51.39 ms	41.37 ms	19.5% faster

hugging-quants/Meta-Llama-3.1-8B-Instruct-AWQ-INT4 — minimal impact (AWQ layers bypass skinny GEMM path):

Workload	Metric	Baseline	Optimized	Change
input=128, output=128	Median TPOT	172.22 ms	169.49 ms	1.6% faster
input=1920, output=128	Median TPOT	173.33 ms	170.54 ms	1.6% faster

TTFT (prefill) is unaffected as the skinny kernels only target batch_size ≤ 4 GEMMs.

Test plan

• test_rocm_wvsplitk_kernel — all 22 parametrized cases pass on gfx1151
• test_rocm_wvsplitk_bias1D_kernel — all 22 parametrized cases pass
• test_rocm_wvsplitk_bias2D_kernel — all 22 parametrized cases pass
• Sanity check: model produces correct answers to math questions in both benchmarks

[gemini-code-assist]

Code Review

This pull request adds support for GFX11 (RDNA3) GPUs to the wvSplitK skinny GEMM kernels, which shows significant performance improvements for decode-phase GEMMs. The changes include adapting to wave32 execution, using new instructions, and updating dispatch logic on both host and device sides. The implementation is mostly correct, but I've identified a few areas for improvement regarding thread-safety and code duplication in the CUDA kernels, which would enhance robustness and maintainability.

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @mgehre-amd.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

[mgehre-amd]

Closed in favor of #34709