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… with PyTorch reference - Truncate RMSNorm output to BF16 before AdaLN affine modulation in Triton kernels - Perform AdaLN scale/shift affine arithmetic in native BF16 to match unfused PyTorch implementation - Ensure indexed gate branch modulation preserves BF16 boundary - Resolves PSNR degradation across multi-step diffusion trajectories (improves final latent PSNR by +1.21 dB) Signed-off-by: BeatSeat <wendavid552@gmail.com>
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| branch = tl.load(branch_ptr + row * stride_branch_row + columns, mask=mask, other=0.0) | ||
| # Match the BF16 residual value consumed by the unfused RMSNorm path. | ||
| updated = (residual + gate * branch).to(tl.bfloat16).to(tl.float32) | ||
| updated = residual + (gate * branch) |
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Set enable_fp_fusion=False; BF16 FMA still skips PyTorch's intermediate rounding.
| residual, gate, branch, weight, shift, scale, indices, eps | ||
| ) | ||
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| torch.testing.assert_close(actual_residual, ref_residual, atol=5e-2, rtol=5e-2) |
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Add an exact rounding regression that fails on the previous kernel.
…unding regression - Pass enable_fp_fusion=False by default for CUDA kernel launches in _launch_row_chunks to prevent BF16 FMA from skipping intermediate rounding on gate * branch - Add test_fused_modulation_exact_rounding_regression covering exact bit-level rounding against unfused PyTorch reference Signed-off-by: BeatSeat <wendavid552@gmail.com>
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Thanks @lishunyang12 for the review! We have pushed an update addressing both points:
Regarding relation with other PRs: |
Purpose
Fixes #7035.
Resolves the deterministic CI regression where the MiniMax-H3 I2VA accuracy test failed with PSNR 33.627597 dB (below the 34.000000 dB threshold on Builds 14708 and 15074).
Background & Root Cause
Before the modulation operator fusion in #6281, MiniMax-H3 evaluated the gated residual update, RMSNorm, and AdaLN affine modulation as separate operations:
PR #6878 restored the BF16 boundary on the gated residual before RMSNorm (
updated = (residual + gate * branch).to(bfloat16)). However, inside the fused Triton kernels invllm_omni/diffusion/attention/ops/minimax_h3_modulation.py:normalizedwas left as an unrounded FP32 intermediate value after RMSNorm.normalized * (1.0 + scale) + shiftwas computed in FP32 instead of native BF16 arithmetic.Even the CPU fallback in #6281 explicitly preserved these BF16 casts:
MiniMax-H3 contains 50 DiT layers. Over a 50-step flow-matching diffusion trajectory, the modulation kernel is invoked 2,500 times. The unrounded FP32 intermediate and affine operations accumulate across the non-linear attention and MLP blocks, causing the deterministic ~0.39 dB degradation down to 33.627 dB.
Key Changes
_rms_norm_indexed_scale_shift_kernel: truncatenormalizedto BF16, and perform the AdaLN scale/shift affine arithmetic in native BF16 (normalized * (scale + 1.0) + shift)._indexed_gate_rms_norm_scale_shift_kernel: ensure both residualupdatedand secondnormalizedtruncate to BF16, evaluating affine modulation in native BF16.tests/diffusion/models/minimax_h3/test_minimax_h3_modulation.py: addtest_fused_modulation_matches_pytorch_referenceto test numerical parity against the PyTorch reference implementation.Test Plan
pytest -v -o addopts="" tests/diffusion/models/minimax_h3/test_minimax_h3_modulation.pyvLLM Version: 0.7.x
vLLM-Omni Commit: 548f286
Test Result
1. Unit Tests
2. A/B Benchmark Results (A800 GPU)
Comparison between current
main(Method B) and this PR's aligned Triton kernel (Method C) against the unfused PyTorch reference (Method A):Single DiT Block
50-Step Diffusion Trajectory (Flow Matching)