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[Test] Fix 4 broken Qwen3-TTS async chunk unit tests#2351

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linyueqian merged 2 commits intovllm-project:mainfrom
linyueqian:fix/qwen3-tts-test-failures
Mar 31, 2026
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[Test] Fix 4 broken Qwen3-TTS async chunk unit tests#2351
linyueqian merged 2 commits intovllm-project:mainfrom
linyueqian:fix/qwen3-tts-test-failures

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@linyueqian linyueqian commented Mar 31, 2026

Summary

Test plan

  • All 36 tests in test_qwen3_tts_async_chunk.py pass (was 32 pass / 4 fail)

Note: these tests are not currently run in CI I add the marker.

Fix test assertions and mocks that fell out of sync with source code
changes in qwen3_tts.py across PRs vllm-project#1930, vllm-project#1852, and vllm-project#2104.

- test_flush_on_finish: `finished` is now a plain bool, not a tensor;
  remove `.item()` call
- test_ic_load_change_mid_request: IC is cached per request since vllm-project#1930;
  update expected emission frames to match current logic
- test_non_async_processor_prepends_ref_code_and_sets_trim_context:
  add missing `finished=True` and `token_ids` to mock (required since vllm-project#2104)
- test_non_async_processor_filters_out_of_range_codec_values: same fix

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

Signed-off-by: linyueqian <linyueqian@outlook.com>
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Comment on lines +180 to +181
p4 = _call(tm, "new_req", n_frames=16)
assert p4 is not None
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P2 Badge Validate IC=16 for high-load new request

The new check in test_ic_load_change_mid_request only asserts that p4 is emitted, but that does not prove the cached/dynamic IC value is 16 as the test comment claims. With chunk_frames=25, frame 16 also emits for IC values 2/4/8, so a regression in load-based IC selection could slip through while this test still passes. Please assert an IC-dependent field (for example left_context_size) so the high-load behavior is actually verified.

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@linyueqian linyueqian added the ready label to trigger buildkite CI label Mar 31, 2026
Add negative assertion: frame 2 must NOT emit under IC=16 (it would
emit under IC=2), proving the load-based IC selection is correct.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

Signed-off-by: linyueqian <linyueqian@outlook.com>
@linyueqian linyueqian force-pushed the fix/qwen3-tts-test-failures branch from 34165a5 to 4ea0e8b Compare March 31, 2026 01:49
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LGTM

@linyueqian linyueqian merged commit 1734c1e into vllm-project:main Mar 31, 2026
7 of 8 checks passed
vraiti pushed a commit to vraiti/vllm-omni that referenced this pull request Apr 9, 2026
Signed-off-by: linyueqian <linyueqian@outlook.com>
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2 participants