[BugFix][Attention] Fix C8 slot mappings under PCP and DCP

[recky-c]

What this PR does / why we need it?

Fixes two C8 cache-write slot mapping issues exposed by PCP and PD disaggregation:

1. PCP can supply an int64 indexer slot_mapping, while the native StoreKvBlockMetadata kernel reads it as int32_t*. Convert only the operator argument to int32, preserving the original metadata.
2. In the combined PCP+DCP SFA path, PCP gathers a full token view before the deferred C8 cache write, but the inherited DCP helper truncated the slot mapping to the local token count. Override the helper in AscendSFAPCPDCPImpl so the gathered KV rows use the complete DCP slot mapping. The ordinary DCP path keeps its existing local slice.

The tests extend the existing indexer dtype coverage and verify that the combined PCP+DCP implementation keeps the complete SFA slot mapping.

Does this PR introduce any user-facing change?

Fixes incorrect indexer and SFA C8 cache writes that can produce incorrect completions when PCP, DCP, and PD disaggregation are combined. No configuration changes.

How was this patch tested?

• Python compilation and git diff --check passed.
• The indexer module tests passed 5/5 in the existing Ascend validation environment.
• Hardware validation used main 28acc786 + [BugFix][Attention] Build SFA indexer DCP metadata independently #16325 (f56cb5b2) + [BugFix][Mooncake] Fix DCP mapping and support P/D-only DCP and PCP+DCP in PD disaggregation #16492 (037f5143), paired with vLLM 84030bbe, GLM-5.2 W4A8C8, MRV2, EP, async scheduling, FULL_DECODE_ONLY, MooncakeConnectorV1, and P TP8 x PCP2 -> D TP8.
• A 48-sample probe confirmed the SFA failure: gathered KV had 4096 rows and the DCP context had 4096 slots, but only 2048 slots were passed to the C8 write. The typical long-request sample had 128 incorrect valid rows.
• After the fixes, P DCP16 -> D DCP1 and P DCP16 -> D DCP8 each passed 28/28 requests with both SFA C8 and indexer C8 enabled. Each run transferred 87,767 external KV tokens. The isolated SFA C8 and combined-C8 boundary suites also passed 3/3.

The hardware results apply to the stated combined checkout and topology.

• vLLM main: vllm-project/vllm@84030bb

[gemini-code-assist]

Summary of Changes

Hello, I'm Gemini Code Assist¹! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed!

This pull request addresses a critical data type mismatch in the indexer C8 slot mapping logic when using PCP. By explicitly casting the slot_mapping to int32 before invoking the StoreKvBlockMetadata kernel, the fix ensures that write destinations are calculated correctly regardless of the input data type, preventing potential cache corruption.

Highlights

• Data Type Mismatch Fix: Resolved an issue where slot_mapping was passed as int64 to a kernel expecting int32, which caused incorrect memory write destinations.
• Regression Testing: Extended unit tests to verify correct handling of both int32 and int64 slot mapping inputs, ensuring robust behavior under PCP.

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[github-actions]

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[gemini-code-assist]

Code Review

This pull request ensures that the slot mapping tensor is explicitly cast to int32 before being passed to the native metadata kernel in the Ascend attention backend, as the kernel expects int32 input. The change includes corresponding updates to the unit tests to verify this behavior across different input dtypes. As there were no review comments provided, I have no feedback to offer.

[kunpengW-code]

Not recommended to make changes in common code paths. Instead, add type conversion at the points where PCP introduces differences.

[github-actions]

This pull request has conflicts, please resolve those before we can evaluate the pull request.