[BugFix][Mamba] Fix PtrOffsetInfo AxisInfo assertion failure - #15032
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Signed-off-by: Lethobenthos20 <3205604419@qq.com>
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Summary of ChangesHello, I'm Gemini Code Assist1! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed! This pull request addresses a critical Triton Ascend assertion failure in the Mamba state pre-copy kernel, which previously hindered V2 Runner inference. The changes include a refactored kernel implementation to resolve the assertion error, the addition of a robust end-to-end test suite to ensure future stability, and the inclusion of detailed documentation to clarify kernel parameters and constraints. Highlights
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Code Review
Suggested PR Title:
[Ops][Feature] Support multi-tile parallelization for Mamba precopy kernel in v2Suggested PR Summary:
### What this PR does / why we need it?
This pull request migrates the `precopy_mamba_align_fused_kernel` to the v2 Triton path and introduces support for multi-tile parallelization (`TEMPORAL_TILES`) to optimize temporal state copying. It also adds documentation and unit tests for the precopy kernel.
Feedback:
A review comment identifies a workload imbalance issue in the temporal state copy logic due to `per_tile_u64` alignment, which can defeat the purpose of parallelization. A more balanced work distribution is suggested.
### Does this PR introduce _any_ user-facing change?
No.
### How was this patch tested?
Tested using the newly added unit test: `tests/e2e/nightly/single_node/ops/singlecard_ops/triton/test_precopy.py`.| per_tile_u64 = tl.cdiv(tl.cdiv(copy_size_u64, TEMPORAL_TILES), COPY_BLOCK_SIZE) * COPY_BLOCK_SIZE | ||
| tile_start = tile_idx.to(tl.int64) * per_tile_u64 | ||
| tile_end = tl.minimum(tile_start + per_tile_u64, copy_size_u64) |
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The current workload distribution for temporal state copy can be inefficient. per_tile_u64 is aligned up to COPY_BLOCK_SIZE, which can cause significant load imbalance among tiles. For instance, with copy_size_u64 = 130, TEMPORAL_TILES = 4, and COPY_BLOCK_SIZE = 128, per_tile_u64 becomes 128. This results in:
- Tile 0 processing 128 elements.
- Tile 1 processing 2 elements.
- Tiles 2 and 3 processing 0 elements.
This largely defeats the purpose of parallelization. A more balanced distribution can be achieved by dividing the work more evenly.
| per_tile_u64 = tl.cdiv(tl.cdiv(copy_size_u64, TEMPORAL_TILES), COPY_BLOCK_SIZE) * COPY_BLOCK_SIZE | |
| tile_start = tile_idx.to(tl.int64) * per_tile_u64 | |
| tile_end = tl.minimum(tile_start + per_tile_u64, copy_size_u64) | |
| work_per_tile = tl.cdiv(copy_size_u64, TEMPORAL_TILES) | |
| tile_start = tile_idx.to(tl.int64) * work_per_tile | |
| tile_end = tl.minimum(tile_start + work_per_tile, copy_size_u64) |
Signed-off-by: Lethobenthos20 <3205604419@qq.com>
Signed-off-by: Lethobenthos20 <3205604419@qq.com>
Signed-off-by: Lethobenthos20 <3205604419@qq.com>
Signed-off-by: Lethobenthos20 <3205604419@qq.com>
Signed-off-by: Lethobenthos20 <3205604419@qq.com>
Signed-off-by: Lethobenthos20 <3205604419@qq.com>
…oject#15032) ### What this PR does / why we need it? This PR fixes the following Triton Ascend assertion failure in the Mamba state pre-copy kernel: ```text PtrOffsetInfo::AxisInfo::operator[]: Assertion `idx < size()` failed ``` This issue was also observed in vllm-project#7103 and vllm-project#10888 . This PR also: - Adds an end-to-end test covering the supported layouts and execution modes. - Adds documentation for the kernel behavior, parameters, constraints, and usage. This is a follow-up to vllm-project#14649. After these changes, V2 Runner inference works correctly. - vLLM version: v0.27.1 - vLLM main: vllm-project/vllm@ba07e4a --------- Signed-off-by: Lethobenthos20 <3205604419@qq.com> Signed-off-by: d30086105 <denghaojie1@h-partners.com>
…oject#15032) ### What this PR does / why we need it? This PR fixes the following Triton Ascend assertion failure in the Mamba state pre-copy kernel: ```text PtrOffsetInfo::AxisInfo::operator[]: Assertion `idx < size()` failed ``` This issue was also observed in vllm-project#7103 and vllm-project#10888 . This PR also: - Adds an end-to-end test covering the supported layouts and execution modes. - Adds documentation for the kernel behavior, parameters, constraints, and usage. This is a follow-up to vllm-project#14649. After these changes, V2 Runner inference works correctly. - vLLM version: v0.27.1 - vLLM main: vllm-project/vllm@ba07e4a --------- Signed-off-by: Lethobenthos20 <3205604419@qq.com>
What this PR does / why we need it?
This PR fixes the following Triton Ascend assertion failure in the Mamba state pre-copy kernel:
This issue was also observed in #7103 and #10888 .
This PR also:
This is a follow-up to [BugFix][Mamba] Fix staged-write kernel and duplicate is_prefilling argument #14649.
After these changes, V2 Runner inference works correctly.

Below is the accuracy of Qwen3.5-27B on the GPQA benchmark.