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Merge branch 'Azure:master' into submodule_update
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vivekrnv authored Jan 14, 2022
2 parents 306e622 + 582a21d commit a9f4d86
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146 changes: 146 additions & 0 deletions device/mellanox/x86_64-mlnx_msn4600c-r0/sensors.conf.a1
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##
## Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES.
## Apache-2.0
##
## Licensed under the Apache License, Version 2.0 (the "License");
## you may not use this file except in compliance with the License.
## You may obtain a copy of the License at
##
## http://www.apache.org/licenses/LICENSE-2.0
##
## Unless required by applicable law or agreed to in writing, software
## distributed under the License is distributed on an "AS IS" BASIS,
## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
## See the License for the specific language governing permissions and
## limitations under the License.
##


# Temperature sensors
bus "i2c-2" "i2c-1-mux (chan_id 1)"
chip "mlxsw-i2c-*-48"
label temp1 "Ambient ASIC Temp"

bus "i2c-7" "i2c-1-mux (chan_id 6)"
chip "tmp102-i2c-*-49"
label temp1 "Ambient Fan Side Temp (air intake)"
chip "tmp102-i2c-*-4a"
label temp1 "Ambient Port Side Temp (air exhaust)"

bus "i2c-15" "i2c-1-mux (chan_id 6)"
chip "tmp102-i2c-15-49"
label temp1 "Ambient COMEX Temp"

# Power controllers
bus "i2c-5" "i2c-1-mux (chan_id 4)"
chip "mp2975-i2c-*-62"
label in1 "PMIC-1 PSU 12V Rail (in1)"
label in2 "PMIC-1 ASIC 0.8V VCORE MAIN Rail (out)"
label temp1 "PMIC-1 Temp 1"
label power1 "PMIC-1 PSU 12V Rail Pwr (in1)"
label power2 "PMIC-1 ASIC 0.8V VCORE MAIN Rail Pwr (out)"
label curr1 "PMIC-1 PSU 12V Rail Curr (in1)"
label curr2 "PMIC-1 ASIC 0.8V VCORE MAIN Rail Curr (out)"
chip "mp2975-i2c-*-64"
label in1 "PMIC-2 PSU 12V Rail (in1)"
label in2 "PMIC-2 ASIC 1.8V VCORE MAIN Rail (out)"
label in3 "PMIC-2 ASIC 1.2V VCORE MAIN Rail (out)"
label temp1 "PMIC-2 Temp 1"
label power1 "PMIC-2 PSU 12V Rail Pwr (in1)"
label power2 "PMIC-2 ASIC 1.8V VCORE MAIN Rail Pwr (out)"
label curr1 "PMIC-2 PSU 12V Rail Curr (in1)"
label curr2 "PMIC-2 ASIC 1.8V VCORE MAIN Rail Curr (out)"
label curr3 "PMIC-2 ASIC 1.2V VCORE MAIN Rail Curr (out)"
chip "mp2975-i2c-*-66"
label in1 "PMIC-3 PSU 12V Rail (in1)"
label in2 "PMIC-3 ASIC 0.85V T0_1 Rail (out)"
label in3 "PMIC-3 ASIC 1.8V T0_1 Rail (out)"
label temp1 "PMIC-3 Temp 1"
label power1 "PMIC-3 PSU 12V Rail Pwr (in1)"
label power2 "PMIC-3 ASIC 0.85V T0_1 Rail Pwr (out)"
label curr1 "PMIC-3 PSU 12V Rail Curr (in1)"
label curr2 "PMIC-3 ASIC 0.85V T0_1 Rail Curr (out)"
label curr3 "PMIC-3 ASIC 1.8V T0_1 Rail Curr (out)"
chip "mp2975-i2c-*-6a"
label in1 "PMIC-4 PSU 12V Rail (in1)"
label in2 "PMIC-4 ASIC 0.85V T2_3 Rail (out)"
label in3 "PMIC-4 ASIC 1.8V T2_3 Rail (out)"
label temp1 "PMIC-4 Temp 1"
label power1 "PMIC-4 PSU 12V Rail Pwr (in1)"
label power2 "PMIC-4 ASIC 0.85V T2_3 Rail Pwr (out)"
label curr1 "PMIC-4 PSU 12V Rail Curr (in1)"
label curr2 "PMIC-4 ASIC 0.85V T2_3 Rail Curr (out)"
label curr3 "PMIC-4 ASIC 1.8V T2_3 Rail Curr (out)"
chip "mp2975-i2c-*-6e"
label in1 "PMIC-5 PSU 12V Rail (in1)"
label in2 "PMIC-5 ASIC 1.2V T0_3 Rail_1 (out)"
label in3 "PMIC-5 ASIC 1.2V T4_7 Rail_2 (out)"
label temp1 "PMIC-5 Temp 1"
label power1 "PMIC-5 PSU 12V Rail Pwr (in1)"
label power2 "PMIC-5 ASIC 1.2V T0_3 Rail_1 Pwr (out)"
label power3 "PMIC-5 ASIC 1.2V T4_7 Rail_2 Pwr (out)"
label curr1 "PMIC-5 PSU 12V Rail Curr (in1)"
label curr2 "PMIC-5 ASIC 1.2V T0_3 Rail_1 Curr (out)"
label curr3 "PMIC-5 ASIC 1.2V T4_7 Rail_2 Curr (out)"

bus "i2c-15" "i2c-1-mux (chan_id 6)"
chip "tps53679-i2c-*-58"
label in1 "PMIC-6 PSU 12V Rail (in1)"
label in2 "PMIC-6 PSU 12V Rail (in2)"
label in3 "PMIC-6 COMEX 1.8V Rail (out)"
label in4 "PMIC-6 COMEX 1.05V Rail (out)"
label temp1 "PMIC-6 Temp 1"
label temp2 "PMIC-6 Temp 2"
label power1 "PMIC-6 COMEX 1.8V Rail Pwr (out)"
label power2 "PMIC-6 COMEX 1.05V Rail Pwr (out)"
label curr1 "PMIC-6 COMEX 1.8V Rail Curr (out)"
label curr2 "PMIC-6 COMEX 1.05V Rail Curr (out)"
chip "tps53679-i2c-*-61"
label in1 "PMIC-7 PSU 12V Rail (in1)"
label in2 "PMIC-7 PSU 12V Rail (in2)"
label in3 "PMIC-7 COMEX 1.2V Rail (out)"
ignore in4
label temp1 "PMIC-7 Temp 1"
label temp2 "PMIC-7 Temp 2"
label power1 "PMIC-7 COMEX 1.2V Rail Pwr (out)"
ignore power2
label curr1 "PMIC-7 COMEX 1.2V Rail Curr (out)"
ignore curr2

# Power supplies
bus "i2c-4" "i2c-1-mux (chan_id 3)"
chip "dps460-i2c-*-58"
label in1 "PSU-1(L) 220V Rail (in)"
ignore in2
label in3 "PSU-1(L) 12V Rail (out)"
label fan1 "PSU-1(L) Fan 1"
ignore fan2
ignore fan3
label temp1 "PSU-1(L) Temp 1"
label temp2 "PSU-1(L) Temp 2"
label temp3 "PSU-1(L) Temp 3"
label power1 "PSU-1(L) 220V Rail Pwr (in)"
label power2 "PSU-1(L) 12V Rail Pwr (out)"
label curr1 "PSU-1(L) 220V Rail Curr (in)"
label curr2 "PSU-1(L) 12V Rail Curr (out)"
chip "dps460-i2c-*-59"
label in1 "PSU-2(R) 220V Rail (in)"
ignore in2
label in3 "PSU-2(R) 12V Rail (out)"
label fan1 "PSU-2(R) Fan 1"
ignore fan2
ignore fan3
label temp1 "PSU-2(R) Temp 1"
label temp2 "PSU-2(R) Temp 2"
label temp3 "PSU-2(R) Temp 3"
label power1 "PSU-2(R) 220V Rail Pwr (in)"
label power2 "PSU-2(R) 12V Rail Pwr (out)"
label curr1 "PSU-2(R) 220V Rail Curr (in)"
label curr2 "PSU-2(R) 12V Rail Curr (out)"

# Chassis fans
chip "mlxreg_fan-isa-*"
label fan1 "Chassis Fan Drawer-1"
label fan2 "Chassis Fan Drawer-2"
label fan3 "Chassis Fan Drawer-3"

5 changes: 3 additions & 2 deletions src/sonic-config-engine/minigraph.py
Original file line number Diff line number Diff line change
Expand Up @@ -510,10 +510,11 @@ def parse_dpg(dpg, hname):
elif ":" in ipnhaddr:
port_nhipv6_map[ipnhfmbr] = ipnhaddr
elif ipnh.find(str(QName(ns, "Type"))).text == 'StaticRoute':
prefix = ipnh.find(str(QName(ns, "AttachTo"))).text
prefix = ipnh.find(str(QName(ns, "AssociatedTo"))).text
ifname = ipnh.find(str(QName(ns, "AttachTo"))).text
nexthop = ipnh.find(str(QName(ns, "Address"))).text
advertise = ipnh.find(str(QName(ns, "Advertise"))).text
static_routes[prefix] = {'nexthop': nexthop, 'advertise': advertise}
static_routes[prefix] = {'nexthop': nexthop, 'ifname': ifname, 'advertise': advertise}

if port_nhipv4_map and port_nhipv6_map:
subnet_check_ip = list(port_nhipv4_map.values())[0]
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -121,8 +121,9 @@
<IPNextHop>
<ElementType>IPNextHop</ElementType>
<Name i:nil="true"/>
<AttachTo>8.0.0.1/32</AttachTo>
<AssociatedTo>8.0.0.1/32</AssociatedTo>
<Address>192.168.1.2,192.168.2.2</Address>
<AttachTo>PortChannel40,PortChannel50</AttachTo>
<Type>StaticRoute</Type>
<Advertise>false</Advertise>
</IPNextHop>
Expand Down Expand Up @@ -212,8 +213,9 @@
<IPNextHop>
<ElementType>IPNextHop</ElementType>
<Name i:nil="true"/>
<AttachTo>8.0.0.1/32</AttachTo>
<Address>192.168.1.2,192.168.2.2</Address>
<AssociatedTo>8.0.0.1/32</AssociatedTo>
<Address>192.168.1.2,192.168.2.2</Address>
<AttachTo>PortChannel40,PortChannel50</AttachTo>
<Type>StaticRoute</Type>
<Advertise>false</Advertise>
</IPNextHop>
Expand Down
4 changes: 2 additions & 2 deletions src/sonic-config-engine/tests/test_cfggen.py
Original file line number Diff line number Diff line change
Expand Up @@ -904,14 +904,14 @@ def test_minigraph_bgp_packet_chassis_static_route(self):
output = self.run_script(argument)
self.assertEqual(
utils.to_dict(output.strip()),
utils.to_dict("{'8.0.0.1/32': {'nexthop': '192.168.1.2,192.168.2.2', 'advertise':'false'}}")
utils.to_dict("{'8.0.0.1/32': {'nexthop': '192.168.1.2,192.168.2.2', 'ifname': 'PortChannel40,PortChannel50', 'advertise':'false'}}")
)

argument = '-m "' + self.packet_chassis_graph + '" -p "' + self.packet_chassis_port_ini + '" -n "' + "asic1" + '" -v "STATIC_ROUTE"'
output = self.run_script(argument)
self.assertEqual(
utils.to_dict(output.strip()),
utils.to_dict("{'8.0.0.1/32': {'nexthop': '192.168.1.2,192.168.2.2', 'advertise':'false'}}")
utils.to_dict("{'8.0.0.1/32': {'nexthop': '192.168.1.2,192.168.2.2', 'ifname': 'PortChannel40,PortChannel50', 'advertise':'false'}}")
)

def test_minigraph_bgp_packet_chassis_vlan_subintf(self):
Expand Down
2 changes: 1 addition & 1 deletion src/sonic-sairedis
2 changes: 1 addition & 1 deletion src/sonic-swss
2 changes: 1 addition & 1 deletion src/wpasupplicant/sonic-wpa-supplicant

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