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Fix SV format around default port value
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@dalance
dalance committed Feb 12, 2025
1 parent d5ce0b2 commit 65bdb7d
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Showing 5 changed files with 83 additions and 36 deletions.
21 changes: 20 additions & 1 deletion crates/aligner/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ pub struct Align {
line: u32,
rest: Vec<(Location, u32)>,
additions: HashMap<Location, u32>,
disable_auto_finish: bool,
pub last_location: Option<Location>,
}

Expand All @@ -55,7 +56,7 @@ impl Align {
pub fn finish_item(&mut self) {
self.enable = false;
if let Some(loc) = self.last_location {
if self.line > loc.line || loc.line - self.line > 1 {
if !self.disable_auto_finish && (self.line > loc.line || loc.line - self.line > 1) {
self.finish_group();
}
self.max_width = u32::max(self.max_width, self.width);
Expand Down Expand Up @@ -140,6 +141,12 @@ impl Aligner {
}
}

pub fn duplicated_token(&mut self, x: &VerylToken, idx: usize) {
for i in 0..self.aligns.len() {
self.aligns[i].duplicated_token(x, idx);
}
}

pub fn space(&mut self, x: usize) {
for i in 0..self.aligns.len() {
self.aligns[i].space(x);
Expand All @@ -162,4 +169,16 @@ impl Aligner {
}
}
}

pub fn enable_auto_finish(&mut self) {
for align in &mut self.aligns {
align.disable_auto_finish = false;
}
}

pub fn disable_auto_finish(&mut self) {
for align in &mut self.aligns {
align.disable_auto_finish = true;
}
}
}
51 changes: 34 additions & 17 deletions crates/emitter/src/emitter.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,8 @@ pub struct Emitter {
generic_map: Vec<Vec<GenericMap>>,
source_map: Option<SourceMap>,
resolved_identifier: Vec<String>,
last_token: Option<VerylToken>,
duplicated_index: usize,
}

impl Default for Emitter {
Expand Down Expand Up @@ -110,6 +112,8 @@ impl Default for Emitter {
generic_map: Vec::new(),
source_map: None,
resolved_identifier: Vec::new(),
last_token: None,
duplicated_index: 0,
}
}
}
Expand Down Expand Up @@ -138,10 +142,12 @@ impl Emitter {
pub fn emit(&mut self, project_name: &str, input: &Veryl) {
namespace_table::set_default(&[project_name.into()]);
self.mode = Mode::Align;
self.duplicated_index = 0;
self.veryl(input);
self.aligner.finish_group();
self.aligner.gather_additions();
self.mode = Mode::Emit;
self.duplicated_index = 0;
self.veryl(input);
}

Expand Down Expand Up @@ -367,6 +373,8 @@ impl Emitter {
self.aligner.token(x);
}
}

self.last_token = Some(x.clone());
}

fn token(&mut self, x: &VerylToken) {
Expand All @@ -377,10 +385,16 @@ impl Emitter {
self.process_token(x, true, None)
}

fn duplicated_token(&mut self, x: &VerylToken, i: usize) {
if self.mode == Mode::Emit {
self.process_token(x, false, Some(i))
fn duplicated_token(&mut self, x: &VerylToken) {
match self.mode {
Mode::Align => {
self.aligner.duplicated_token(x, self.duplicated_index);
}
Mode::Emit => {
self.process_token(x, false, Some(self.duplicated_index));
}
}
self.duplicated_index += 1;
}

fn align_start(&mut self, kind: usize) {
Expand All @@ -405,12 +419,6 @@ impl Emitter {
}
}

fn align_duplicated_token(&mut self, kind: usize, x: &VerylToken, i: usize) {
if self.mode == Mode::Align {
self.aligner.aligns[kind].duplicated_token(x, i);
}
}

fn case_inside_statement(&mut self, arg: &CaseStatement) {
let (prefix, force_last_item_default) = self.cond_type_prefix(&arg.case.case_token.token);
self.token(&arg.case.case_token.append(&prefix, &None));
Expand Down Expand Up @@ -920,6 +928,12 @@ impl Emitter {
.iter()
.any(|y| x.name() == y.identifier.identifier_token.token.text)
});

// Disable aligner auto finish based on line number
// because line number of default values are not reliable
self.aligner.disable_auto_finish();

let src_line = self.src_line;
for (i, port) in unconnected_ports.enumerate() {
if i >= 1 || !connected_ports.is_empty() {
self.str(",");
Expand All @@ -928,17 +942,26 @@ impl Emitter {

let property = port.property();
self.str(".");
self.clear_adjust_line();
self.align_start(align_kind::IDENTIFIER);
self.token(&port.token);
self.align_finish(align_kind::IDENTIFIER);
self.space(1);
self.str("(");
self.align_start(align_kind::EXPRESSION);
self.expression(&property.default_value.unwrap());

// Create a dummy token from the last token in expression to add align information
let token = self.last_token.as_ref().unwrap().replace("");
self.duplicated_token(&token);

self.align_finish(align_kind::EXPRESSION);
self.str(")");
}

self.aligner.enable_auto_finish();

self.src_line = src_line;
self.generic_map.pop();
}

Expand Down Expand Up @@ -3018,12 +3041,7 @@ impl VerylWalker for Emitter {
self.align_finish(align_kind::EXPRESSION);
} else {
self.align_start(align_kind::EXPRESSION);
self.align_duplicated_token(
align_kind::EXPRESSION,
&arg.identifier.identifier_token,
0,
);
self.duplicated_token(&arg.identifier.identifier_token, 0);
self.duplicated_token(&arg.identifier.identifier_token);
self.align_finish(align_kind::EXPRESSION);
}
self.str(")");
Expand Down Expand Up @@ -3074,8 +3092,7 @@ impl VerylWalker for Emitter {
} else {
let token = emitting_identifier(arg.identifier.as_ref());
self.align_start(align_kind::EXPRESSION);
self.align_duplicated_token(align_kind::EXPRESSION, &token, 0);
self.duplicated_token(&token, 0);
self.duplicated_token(&token);
self.align_finish(align_kind::EXPRESSION);
}
self.str(")");
Expand Down
2 changes: 1 addition & 1 deletion testcases/map/testcases/sv/73_port_default_value.sv.map
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36 changes: 21 additions & 15 deletions testcases/sv/73_port_default_value.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -6,40 +6,46 @@ module veryl_testcase___Module73A__0 (
input logic i_a,
input logic i_b,
input logic i_c,
output logic o_d
output logic o_d,
output logic o_e
);
always_comb o_d = 0;
always_comb o_e = 0;
endmodule
module veryl_testcase___Module73A__1 (
input logic i_a,
input logic i_b,
input logic i_c,
output logic o_d
output logic o_d,
output logic o_e
);
always_comb o_d = 0;
always_comb o_e = 0;
endmodule

module veryl_testcase_Module73B;
logic _d ;

veryl_testcase___Module73A__0 u0 (
.i_a (veryl_testcase_Package73::A),
.i_b (0 ),
.i_c (0),
.o_d ( )
)
;
.i_c (0 ),
.o_d ( ),
.o_e ( )
);
veryl_testcase___Module73A__1 u1 (
.i_a (veryl_testcase_Package73::A),
.i_b (1 ),
.i_c (0),
.o_d ( )
)
;
.i_c (0 ),
.o_d ( ),
.o_e ( )
);
veryl_testcase___Module73A__1 u2 (
.i_a (0),
.i_b (0),
.i_c (0),
.o_d ( )

.i_a (0 ),
.i_b (0 ),
.o_d (_d),
.i_c (0 ),
.o_e ( )
);
endmodule
//# sourceMappingURL=../map/testcases/sv/73_port_default_value.sv.map
9 changes: 7 additions & 2 deletions testcases/veryl/73_port_default_value.veryl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,15 +7,20 @@ module Module73A::<B: const> (
i_b: input logic = B ,
i_c: input logic = 0 ,
o_d: output logic = _ ,
o_e: output logic = _ ,
) {
assign o_d = 0;
assign o_e = 0;
}

module Module73B {
var _d: logic;

inst u0: Module73A::<0>;
inst u1: Module73A::<1>;
inst u2: Module73A::<1> (
i_a: 0,
i_b: 0,
i_a: 0 ,
i_b: 0 ,
o_d: _d,
);
}

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