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cpu: risc-v: convolution: Vectorize post-ops with RVV intrinsics #3852

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Merged
vpirogov merged 5 commits into from
Oct 17, 2025
Merged

cpu: risc-v: convolution: Vectorize post-ops with RVV intrinsics #3852

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6ec16df
cpu: rv64: convolution: Vectorize post-ops with RVV intrinsics
xiazhuozhao Sep 1, 2025
0e89895
cpu: rv64: convolution: optimize ncsp relu and adjust nspc impl
xiazhuozhao Sep 10, 2025
b9425ec
cpu: rv64: conv: Refactor validation logic and cleanup
xiazhuozhao Sep 15, 2025
b701411
cpu: risc-v: convolution: Add a newline at the end of the file.
xiazhuozhao Oct 3, 2025
25468f0
cpu: risc-v: Restore specific checks in post_ops_ok for gemm convolution
xiazhuozhao Oct 15, 2025
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6 changes: 6 additions & 0 deletions src/cpu/cpu_convolution_list.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,11 @@ using namespace dnnl::impl::cpu::x64;
#include "cpu/aarch64/acl_winograd_convolution.hpp"
#endif
using namespace dnnl::impl::cpu::aarch64;
#elif DNNL_RV64
#if defined(DNNL_RISCV_USE_RVV_INTRINSICS)
#include "cpu/rv64/rvv_gemm_convolution.hpp"
using namespace dnnl::impl::cpu::rv64;
#endif // DNNL_RISCV_USE_RVV_INTRINSICS
#endif

namespace dnnl {
Expand Down Expand Up @@ -160,6 +165,7 @@ const std::map<pk_dt_impl_key_t, std::vector<impl_list_item_t>> &impl_list_map()
CPU_INSTANCE_AARCH64(brgemm_1x1_convolution_fwd_t<sve_128>)
CPU_INSTANCE_AARCH64(brgemm_convolution_fwd_t<sve_128>)
CPU_INSTANCE_X64(jit_uni_ncsp_convolution_fwd_t)
CPU_INSTANCE_RV64GCV(riscv_gemm_convolution_fwd_t)
CPU_INSTANCE(gemm_convolution_fwd_t)
CPU_INSTANCE(ref_convolution_fwd_t)
CPU_INSTANCE(ref_fused_convolution_fwd_t)
Expand Down
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