cpu: rv64: gemm: add bf16 gemm SIMD optimization with RISC-V V Extension#3845
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ryanle1017 wants to merge 1 commit intouxlfoundation:mainfrom
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cpu: rv64: gemm: add bf16 gemm SIMD optimization with RISC-V V Extension#3845ryanle1017 wants to merge 1 commit intouxlfoundation:mainfrom
ryanle1017 wants to merge 1 commit intouxlfoundation:mainfrom
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Co-authored-by: Fei Zhang <zhangfei@iscas.ac.cn>
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Description
This PR introduces a SIMD-optimized
bfloat16GEMM kernel for the RISC-V 64-bit architecture, leveraging the RISC-V Vector (V) Extension. This work extends the foundational f32 GEMM implementation from PR #3785, enabling high-performance mixed-precision computations.The primary motivation is to accelerate inference on emerging RISC-V platforms. As
bfloat16becomes a critical data type for modern deep learning models, offering significant memory bandwidth savings with a dynamic range comparable tof32, this optimized kernel fills a crucial performance gap.This implementation focuses on the
bf16:bf16:f32data type combination (bfloat16inputs,float32accumulation and output), which is a common and numerically robust approach for mixed-precision GEMM.Key Changes
rvv_gemm_bf16bf16f32) specifically designed forbfloat16inputs andfloat32outputs/accumulation.src/cpu/gemm/gemm.cppis updated to routebf16bf16f32requests to the new RVV kernel when running on a compatible RISC-V platform.platform::mayiuse_bf16()to correctly detect and enablebfloat16support when RVV intrinsics are available for RISC-V.Checklist
General
make testandmake test_benchdnn_*) pass locally for each commit?Performance improvements
All performance data was measured on a
--TODO
The performance baseline is the default
ref_gemmimplementation in the oneDNN main branch. Below are some example performance benchmarks for different problem sizes.Matmul Primitives Performance(
--dt=bf16:bf16:f32)New features
Bug fixes
RFC PR