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dpu: MRAM pointer 64-bit access correctly uses SoftCache mechanism
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Fix #5
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Jordi Chauzi committed Aug 5, 2019
1 parent abac275 commit 7469549
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Showing 2 changed files with 49 additions and 6 deletions.
15 changes: 9 additions & 6 deletions llvm/lib/Target/DPU/DPUInstrInfo.td
Original file line number Diff line number Diff line change
Expand Up @@ -72,8 +72,6 @@ def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
return isOrEquivalentToAdd(N);
}]>;

def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;

class wram_load_frag<PatFrag base_load> : PatFrag<(ops node:$ptr), (base_load node:$ptr), [{
return IsALoadFromAddrSpace(N, DPUADDR_SPACE::WRAM);
}]>;
Expand All @@ -82,6 +80,8 @@ class wram_store_frag<PatFrag base_store> : PatFrag<(ops node:$val, node:$ptr),
return IsAStoreToAddrSpace(N, DPUADDR_SPACE::WRAM);
}]>;

def wram_loadi64 : PatFrag<(ops node:$ptr), (i64 (wram_load_frag<load> node:$ptr))>;

multiclass WramLoadXPat<ImmOperand LdTy, PatFrag LoadOp, DPUInstruction Inst> {
def : Pat<(LdTy (wram_load_frag<LoadOp> SimpleRegOrCst:$ra)), (Inst SimpleRegOrCst:$ra, 0)>;
def : Pat<(LdTy (wram_load_frag<LoadOp> AddrFI:$ra)), (Inst AddrFI:$ra, 0)>;
Expand Down Expand Up @@ -633,7 +633,7 @@ let usesCustomInserter = 1 in {
def WRAM_LOAD_DOUBLErm : PseudoDPUInstruction<
(outs GP64_REG:$dc), (ins MEMri24:$addr),
"",
[(set i64:$dc, (loadi64 ADDRESS_IN_STACK:$addr))]>;
[(set i64:$dc, (wram_loadi64 ADDRESS_IN_STACK:$addr))]>;

def WRAM_LOAD_DOUBLE_ALIGNEDrm : PseudoDPUInstruction<
(outs GP64_REG:$dc), (ins MEMri24:$addr),
Expand Down Expand Up @@ -700,8 +700,6 @@ let usesCustomInserter = 1 in {
[(MramStore64 i64:$db, ADDRESS_IN_STACK:$addr)]
>;

// TODO: MRAM LOAD DOUBLE

def MRAM_LOADmr : MRAM_LOAD_X_mr<mram_load>;

def MRAM_LOAD_U8mr : MRAM_LOAD_X_mr<mram_zextloadi8>;
Expand All @@ -715,4 +713,9 @@ let usesCustomInserter = 1 in {
// Notice that this applies to "anyext from iXX, where XX is 8 or 16"
def MRAM_LOAD_X8mr : MRAM_LOAD_X_mr<mram_extloadi8>;
def MRAM_LOAD_X16mr : MRAM_LOAD_X_mr<mram_extloadi16>;
}

def MRAM_LOAD_DOUBLEmr: PseudoDPUInstruction<
(outs GP64_REG:$dc), (ins MEMri24:$addr),
"",
[(set i64:$dc, (mram_load ADDRESS_IN_STACK:$addr))]>;
}
40 changes: 40 additions & 0 deletions llvm/lib/Target/DPU/DPUTargetLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2312,6 +2312,44 @@ EmitMramSubLoadWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB,
return BB;
}

static MachineBasicBlock *
EmitMramLoadDoubleWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) {
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
DebugLoc dl = MI.getDebugLoc();
MachineFunction *F = BB->getParent();

MachineRegisterInfo &RI = F->getRegInfo();
unsigned WramCacheAddrReg = RI.createVirtualRegister(&DPU::GP_REGRegClass);
unsigned MramAddrReg = RI.createVirtualRegister(&DPU::GP_REGRegClass);

// todo __sw_cache_buffer should have abstract representation

BuildMI(*BB, MI, dl, TII.get(DPU::ADDrri), WramCacheAddrReg)
.addReg(DPU::ID8)
.addExternalSymbol("__sw_cache_buffer");

if (MI.getOperand(2).getImm() == 0) {
BuildMI(*BB, MI, dl, TII.get(DPU::COPY), MramAddrReg).add(MI.getOperand(1));
} else {
BuildMI(*BB, MI, dl, TII.get(DPU::ADDrri), MramAddrReg)
.add(MI.getOperand(1))
.add(MI.getOperand(2));
}

BuildMI(*BB, MI, dl, TII.get(DPU::LDMArri))
.addReg(WramCacheAddrReg)
.addReg(MramAddrReg)
.addImm(0);

BuildMI(*BB, MI, dl, TII.get(DPU::LDrri))
.add(MI.getOperand(0))
.addReg(WramCacheAddrReg)
.addImm(0);

MI.eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}

static MachineBasicBlock *
EmitAlignedStoreWramDoubleRegisterWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *BB) {
Expand Down Expand Up @@ -3482,6 +3520,8 @@ DPUTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case DPU::MRAM_LOAD_U32mr:
case DPU::MRAM_LOADmr:
return EmitMramSubLoadWithCustomInserter(MI, BB, 4, DPU::LWrri);
case DPU::MRAM_LOAD_DOUBLEmr:
return EmitMramLoadDoubleWithCustomInserter(MI, BB);
case DPU::WRAM_STORE_DOUBLErm:
return EmitUnalignedStoreWramDoubleRegisterWithCustomInserter(MI, BB);
case DPU::WRAM_STORE_DOUBLE_ALIGNEDrm:
Expand Down

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