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Rearchitecting the tool flow (Not ready to merge) #1

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Rearchitecting the tool flow (Not ready to merge) #1

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Commits on Mar 23, 2020

  1. Updated scala version

    @d0cd
    d0cd committed Mar 23, 2020
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  2. Reorganized project structure

    @d0cd
    d0cd committed Mar 23, 2020
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  3. Added base for a general verification language

    @d0cd
    d0cd committed Mar 23, 2020
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  4. Created annotations for circuit analysis passes; fixed compiler error… 

    …s in verification lang
    @d0cd
    d0cd committed Mar 23, 2020
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Commits on Mar 24, 2020

  1. Created CollectCircuitInfo transform

    @d0cd
    d0cd committed Mar 24, 2020
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  2. Added CollectModuleInfo transform and decoupled UCLID logic; cleaned … 

    …up CollectInfo.scala
    @d0cd
    d0cd committed Mar 24, 2020
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  3. Added ExpandMemoryWires transform; minor changes to CollectModuleInfo

    @d0cd
    d0cd committed Mar 24, 2020
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  4. Split structure of ModuleInfoAnnotation; made other passes compatible… 

    … with the change
    @d0cd
    d0cd committed Mar 24, 2020
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  5. Added ComputeClockDomain pass (needs reimplementation); moving to emi… 

    …ssion
    @d0cd
    d0cd committed Mar 24, 2020
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  6. Modified structure of verification stages

    @d0cd
    d0cd committed Mar 24, 2020
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  7. Added scaffolding for emitting UCLID, need to figure out the emission… 

    … API in FIRRTL
    @d0cd
    d0cd committed Mar 24, 2020
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