Hierarchical write_ilm options for top_layer/pg_pins (#819)

Currently, this uses the auto-power-straps by_tracks pin_layers
option to determine the top_layer and pg_pin_layers

hammer/config/defaults.yml

@@ -608,6 +608,7 @@ par:
       # type: str
 
       pin_layers: [] # Layers to put power pins on
+      # This is also used in bottom-up hierarchical flows to configure LEF generation
       # type: List[str]
 
       strap_layers: [] # List of layers on which to place power straps (std cell rail layer is implied - do not include it)

hammer/par/innovus/__init__.py

@@ -848,7 +848,16 @@ def write_ilm(self) -> bool:
         self.verbose_append("time_design -post_route")
         self.verbose_append("time_design -post_route -hold")
         self.verbose_append("check_process_antenna")
-        self.verbose_append("write_lef_abstract -5.8 {top}ILM.lef".format(top=self.top_module))
+
+        # Currently, this assumes auto-power-straps by_tracks, and uses the pg pin layer
+        # to determine the top layer in the generated LEF
+        assert self.get_setting("par.generate_power_straps_method") == "by_tracks", "Hierarchical write_ilm currently requires auto power_straps by_tracks"
+        top_layer = self.get_setting("par.generate_power_straps_options.by_tracks.pin_layers")
+        assert len(top_layer) == 1, "Hierarchical write_ilm requires 1 pin layer specified"
+        self.verbose_append("write_lef_abstract -5.8 -top_layer {top_layer} -stripe_pins -pg_pin_layers {{{top_layer}}} {top}ILM.lef".format(
+            top=self.top_module,
+            top_layer=top_layer[0]
+        ))
         self.verbose_append("write_ilm -model_type all -to_dir {ilm_dir_name} -type_flex_ilm ilm".format(
             ilm_dir_name=self.ilm_dir_name))
         # Need to append -hierarchical after get_pins in SDCs for parent timing analysis